High speed data classification system

ABSTRACT

An optical network packet classification architecture is disclosed that addresses the packet classification requirements for OC-768 optical routers and beyond. The herein disclosed system is used for ultra-high speed packet classification of optical data at either the serial data stream level for maximum performance, or after it has been converted into parallel words of data. The presently preferred embodiment of the invention provides a system that operates in the receive path, where electronic data are provided by the optical interface to the data framer. The invention incorporates unique features into a traditional optical data framer chip and relies on a complex ASIC to permit the user to differentiate between up to 10,000 different patterns at ultra-high speeds. One purpose of the general purpose system disclosed herein is to eliminate the need for costly and power consumptive content addressable memory systems, or customer pattern specific ASICs, to perform network packet classification. The system operates on a principle of adaptive programmable randomization to permit a differentiation between the input vectors to be made. The invention dramatically reduces the processing burden required by high-speed optical routers or switches.

BACKGROUND OF THE INVENTION

1. Technical Field

The invention relates to computer networks. More particularly, theinvention relates to an information processing system.

2. Description of the Prior Art

Communication between computers over the Internet can be compared to thedelivery of mail and packages by the United States Postal Service. Usersaccess the Internet through a variety of options, e.g. phone modems, DSLmodems, cable modems, T-1 lines, local area networks, wireless networks,and wide area networks.

In the world of the U.S. Postal Service, access to the mail system couldbe through a mail-slot in the door of your home, a mailbox at the streetin front of your home, a post office box on a street corner, a postoffice counter, or a post office box. By analogy, each user of theInternet is assigned an address, and the Internet infrastructure learnshow to deliver messages intended for them.

In the world of the Postal Service, the zip code, city, street, andstreet number are used progressively to determine how to route anddeliver the mail. Users of the Internet rely on various networkingprotocols to transfer messages between computers.

In the world of the Postal Service, the protocols for delivering themail include First Class Delivery, Next Day Air, Parcel Post, and Bulk.In the world of the Internet, messages are sent in packets, as opposedto the letters that are sent in the world of the Post Office. Thesepackets contain information necessary for delivery, and this informationis found in the Packet Header. This packet header includes therecipient's addresses and the sender's address, as well as the deliverymethod and style of message. The packet header is comparable to all ofthe information that is visible on the outside of a letter or package,i.e. recipient's address, return address, mail type, and specifichandling instructions, such as FRAGILE. The remainder of an Internetpacket contains user data. This user data is comparable to what is foundinside an envelope or package. The Internet infrastructure has no moreneed to see the user data to route and deliver the message to theintended computer accurately than the post office has to open the mailit handles to figure out where to send it. Table A below shows a typicalInternet packet.

TABLE A Typical Internet Packet Packet Header Data Payload

As computers are tied together over the World Wide Web, the physicalconnections between the computers look like a giant spider web. Thethick strands of this web transfer huge numbers of packets between bigcities to move them along their way. This is comparable to the air ortruck traffic carrying millions of letters between postal hubs. At eachconnection point on the World Wide Web, a sorting function must beperformed to determine which direction a message should be sent. Thissorting of packets is similar to the process where high-speed postalsorters scan letters to determine their addresses and figure out whichdirection to send them. Sorting of data packets is often referred to aspacket classification

An optical router is a device that has many input/output (I/O) ports orconnections. Each I/O port connects through an optical fiber to anotheroptical router, optical switch, or optical adapter that can be located along distance geographically from the first device. In simplistic terms,the purpose of an optical router is to receive data packets on each I/Oport, to interpret the headers within the packet, and to route thepacket out the appropriate I/O port towards the destination computer. Ifan optical router is unable to sort packets quickly enough, packetsbackup and are potentially lost by the router. In such case, theInternet slows down and computer users may lose their connections. Asmore and more people use the Internet, the situation internal to theoptical routers that makeup part of the Internet infrastructure canstart to look as chaotic as the Post Office at Christmas time.

The goal of an optical router is to interpret the packet header for eachreceived packet as fast as possible so that the packets can be sent outthe correct I/O port. This avoids delays, backups, and potentially lostpackets. One problem is that thousands of different users can be sendingmessages through a router at the same time, and the packets all need tobe sorted and routed differently. Table B below shows how the number ofpossible headers that can be received increases dramatically as thenumber of bits in the packet header increases.

TABLE B Possible Headers versus Header Bit Length Packet Header BitLength Possible Headers 8 256 16 65536 32 4.29 E9 64 1.84 E19 128 3.40E38 256 1.16 E77 512 1.34 E154 1024 1.80 E308

The problem of receiving a packet and identifying critical headerinformation to decide where to route the packet is much like finding aneedle in a haystack. Initially, routers used microprocessors and largelookup tables in memory to search for addresses and header information.Later, as data rates increased, system designers moved to contentaddressable memories (CAMs) to allow the received packet header to becompared to all previously analyzed packet headers simultaneously. Thearchitecture of a CAM permits the user to apply the received headerinformation to the memory and to determine to which location(s) itmatches.

Because the performance of CAM's could not keep up with ultra-high speedrouter implementations, some manufacturers switched to custom ASICs(Application Specific Integrated Circuits) to evaluate packet headers ina rapid fashion.

Optical networking is a significant business opportunity because of thetremendous increases in data bandwidth requirements resulting from theincreasing use of Internet. The capability of optical fibers to transmitand receive data exceeds the capability of electronic andelectro-optical interface products to keep up with increasing datarates. Presently, OC-192 standard networks that operate at 10 Gbit/secare beginning to be used. Presently available optical routers addressthe need attendant with processing and routing packets from OC-192systems.

Existing Optical Network Packet Classification Schemes

High performance optical routers have been generally implemented usingeither CAMs or custom ASICS to perform packet classification. The customASIC approach must rely on filtering and interpreting some subset ofpossible packet data patterns to determine how to route packets. Theapproach is inflexible and may be difficult to scale with new standardsand new protocols. The CAM approach is more flexible and is popular inhigh end routers. CAMs are designed to be cascaded so that greaternumbers of data bits can be analyzed. CAMs are designed to permitvarious levels of “don't care” functionality that has increased theirflexibility and usefulness.

CAM Based Classification Systems

A typical router is shown in FIGS. 1 a and 1 b and is used to describesome of the problems associated with increasing data rates to 10Gbit/sec, 40 Gbit/sec, and beyond. In FIG. 1 a, the optical interface 11translates the light stream into electrical signals and vice-versa. Inthe receive mode, the data framer 12 is responsible for extracting aserial receive clock and corresponding serial receive data stream. Theserial data stream must then be converted into a parallel sequence ofwords that correspond to a packet. The parallel sequence of words can beoperated on by a network processor 13, and eventually routed into theswitch fabric 14 where they are sent to the appropriate destination.

Custom ASIC Solution (Juniper Networks ASIC2)

Juniper Networks (Sunnyvale, Calif.) provides high performance routersthat use a custom ASIC solution that is marketed as the Juniper NetworksASIC2. The Juniper Networks ASIC2 in conjunction with the Juniper“Junos” software allows up to 40 M packets/sec to be forwarded in theJuniper system. From Juniper's data sheets, the following:

-   -   Juniper's routers leave the packet in the shared memory and move        only a packet pointer through the queues. When packets arrive        they are immediately placed in distributed shared memory where        they remain until being read out of memory for transmission.        This shared memory is completely nonblocking, which in turn,        prevents head-of-line blocking.

FIG. 1 b shows how a Juniper router is believed to be implemented, andhow it relies on a very high speed shared SRAM 17 where packets arestored and operated on. This architecture avoids the movement of packetsaround in memory which can take up a considerable amount of time.

CAM and Custom ASIC Shortcomings for Packet Classification of OC-192 andBeyond

A variety of problems are beginning to plague CAM and customer ASICbased systems as data rates are moving to OC-192 (10 Gbits/sec) andOC-768 (40 Gbits/sec). Some of the biggest problems have to do with rawforwarding throughput, which is related to how many packets per secondcan be processed; latency, which is related to the absolute delaythrough a router; system power consumption; and board area. A keycomponent of packet latency through a router is the time necessary toperform packet classification. As latency increases, the chances ofexperiencing upper level networking protocol timeouts for a packetincrease.

Typical CAM structures have a width that is associated with how manybits the user desires to analyze, and a depth that is based on thenumber of possible patterns that the user wishes to differentiatebetween. CAMs are cascadable to meet both the width and depth that isrequired. The downside of cascading is that it costs money, increasesboard area, and increases power consumption. On the other hand, theASIC2 solution from Juniper Networks does not appear to be cascadable.It appears to operate on data in the SRAM, and permits qualifiedsearches on only certain fields and bits. This limits the ASIC2 solutionapproach when new search criteria are desired to be used.

Packet Classification Forwarding Rate and Latency Issues

The issues of forwarding rate and latency are intertwined and need to beaddressed together. There are two significant architectural issues thataffect forwarding rate and latency, i.e. the design of a packet's dataflow through the system, and the underlying performance of the packetclassification hardware.

In a CAM based system, such as that in FIG. 1 a, parallel data from thedata framer and any associated memory must be moved by the networkprocessor or custom hardware into the CAM 15 for analysis. This is doneafter a packet has been received. This data must be moved quickly oradditional latency is introduced. Table C below shows how the spacingbetween words in a received data pattern decreases as the serial datarate is increased. Each word that must be transferred to the CAMrequires a read from the data framer's memory and a write to the CAM. Inthe case of very short data packets, which are the hardest for a routerto handle, most of the packets must be transferred into the CAM. Even ifreading from the data framer and writing to the CAM could be each donein a single cycle, this would require a dedicated 1/(3.2 nsec/2)=625 MHzprocessor and memory system to keep up at OC-192 rates with a 32 bitdata framer. The problem becomes four times worse at OC-768 speeds andwould require a processor and memory system running at 2.5 GHz.

TABLE C Data Framer Output Word Separation vs. Data Rate OC-48 OC-192OC-768 2.5 Gbit/sec 10 Gbit/sec 40 Gbit/sec Output Separation 12.8 nsec3.2 nsec 0.8 nsec (for a data Framer with a 32 Bit Output Word) OutputSeparation 25.6 nsec 6.4 nsec 1.6 nsec (for a data Framer with a 64 BitOutput Word)

In addition to the delays and uncertainty associated with transferringthe data from the data framer into the CAM memory, there is the delay ofthe CAM memory in processing the data once the final word has beenpresented. Typical CAM memories have delays of approximately 100 nsecfrom application of data to input match. This is expected to improve asCAM technologies improve, but is not likely to experience anything closeto four times improvements as users move from OC-192 to OC-768. Due tothis inherent access delay of CAM memories, the delay in receivingrouting information becomes worse relative to data rate as speedsincrease. This results in the need to increase queue's and storagedepths to account for buffering data prior to knowing to where it shouldbe routed.

Present CAM classification systems are claimed to operate at full linedata rates. The problem is that they require packets to be received,staged, and then sent into the classification engine to determine anappropriate route or other required information. This delay increasesthe latency through the router for a packet to be sent. Eventually, thislatency through a router can start to impact connections going throughthe router and can result in higher layer timeouts. As new CAMtechnologies are implemented, the focus is on increasing size andmaintaining access time. Therefore, the access time is not scalinganywhere near as quickly as data rate.

In the case of the Juniper Network's ASIC2 solution (FIG. 1 b), it isdifficult to glean detailed technical information from their website. Itappears as though the ASIC2 approach operates on a packet that is inshared SRAM. The appropriate bits of this packet appear to betransferred into the ASIC2 18 so that it can perform packetclassification. This transfer has measurable delays associated with it,depending upon the hardware architecture and the memory speed. If theshared SRAM has a 10 nsec access time, and it is 64 bits wide, it takes40 nsec to transfer 256 bits into the ASIC2 chip before a classificationbegins. The ASIC2 specification identifies a performance metric thatprovides a raw maximum 40 Million Packets/se of classificationperformance, which implies a classification every 25 nsec. This could befor packets requiring only a single data write into the ASIC2 partbecause it is a top end specification. Even in the Juniper ASIC2solution, the parallel movement of data into the ASIC2 part must limitthe performance of the overall packet classification system. The ASIC2solution has a much lower inherent latency than present CAM solutions,but it's packet classification time varies based on packet movement andmemory access prioritization. Even with it's higher performance, theASIC2 solution does not begin packet classification until well after adata packet has been received. As data rates continue to increase thisbecomes an architectural limitation for the ASIC2 custom approach.

Power Consumption and Board Area Issues.

The overall power consumption of a router system increases because thenetwork processor speed must be increased to process higher data rates.In addition, CAM memories have a static current draw that must beaccounted for and scaled up. As an example, a currently availablenetwork data base search engine using CAM technology draws 6 Amps @1.5Volts running at 1000 MHz. This is an extremely high 9 Watts on a singlechip. This impacts the usability of this solution in applications wherespace is tight and power is limited. It is noted the increased powerconsumption also raises issues of heat dissipation that must beaddressed.

As packet classification searches farther into a packet, such as to 512or 1024 bits deep, CAM based solutions require multiple parts to beoperated in parallel. This significantly increases power consumption andboard area. In the case of the ASIC2 solution, increasing the depth ofthe classification requires an entirely new part to be developed. Inaddition, the ASIC2 solution could require greater memory bandwidthswith higher speeds, which would entail more parts and larger ASICs.

It would be advantageous to provide an improved system for ultra-highspeed packet classification of optical data that has been framed into aserial data stream.

SUMMARY OF THE INVENTION

The herein disclosed invention provides a system that permits flexible,low latency, ultra-wide, and deep classification of high speed data. Apresently preferred embodiment of the invention comprises an opticalnetwork packet classification architecture that addresses the packetclassification requirements for OC-768 optical routers and beyond.Packet classification involves understanding the source and destinationof a packet, as well as interpreting information within the packetheader to determine what the optical network processor should do withthe packet. As the data rates of optical networks move up to OC-768 andbeyond, the job of performing packet classification is becomingincreasingly more difficult. The approach used in the herein disclosedsystem allows for true “Light Speed” classification of optical datapackets.

The herein disclosed system is used for ultra-high speed packetclassification of optical data that has been framed into a serial datastream. The presently preferred embodiment of the invention provides asystem that operates in the receive path, where electronic data areprovided by the optical interface to the data framer. The preferredembodiment of the invention incorporates unique features into atraditional optical data framer chip and relies on a complex ASIC topermit the user to differentiate between up to 10,000 different patternsat light speed. One purpose of the general purpose system disclosedherein is to eliminate the need for costly and power consumptive contentaddressable memory systems, or customer pattern specific ASICs, toperform network packet classification. The system operates on aprinciple of adaptive programmable randomization to permit adifferentiation between the input vectors to be made. The inventiondramatically reduces the processing burden required by high-speedoptical routers or switches.

The modified data framer that is used in the preferred system isreferred to herein as the novel data framer; the complex ASIC that isused to control the adaptive programmable randomizer is referred toherein as the ASIC, both of which are discussed in greater detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 a is a block schematic diagram of a typical router that usesCAMs;

FIG. 1 b is a block schematic diagram of the architecture of an ASICbased router;

FIG. 2 a is a block schematic diagram that shows an optical router orswitch using the herein disclosed system;

FIG. 2 b is a block schematic diagram that shows an optical router orswitch using the herein disclosed system in which the parallel mode ofclassification is used;

FIG. 3 is a block schematic diagram that shows a novel data frameraccording to the invention;

FIG. 4 is a block schematic diagram that shows a custom ASIC accordingto the invention;

FIG. 5 is a block schematic diagram that shows an embodiment of theinvention in which an optical delay line is used to make a decision asto where to route a packet prior to the packet arriving at the end ofthe delay line;

FIG. 6 is a block schematic diagram that shows the system on a routerbackbone;

FIG. 7 is a block schematic diagram that shows an unsynchronized datapattern extraction system according to the invention;

FIGS. 8 a and 8 b provide a block schematic diagram of a primary andsecondary randomizer circuit according to the invention;

FIG. 9 is a block schematic diagram that shows enable and ON/OFFcircuitry according to the invention;

FIG. 10 is a block schematic diagram that shows programmable maskingcircuitry according to the invention;

FIG. 11 is a block schematic diagram that shows programmable outputregister synchronization and queue according to the invention;

FIG. 12 is a block schematic diagram that shows forced masking andwalking one's injection for INPUT_REG_BANKn according to the invention;

FIG. 13 is a block schematic diagram that shows programmable maskingcircuitry according to the invention;

FIG. 14 is a block schematic diagram that shows an example ofqstateout[0] generation for an individual stage for the MEGA XORapproach according to the invention;

FIG. 15 is a block schematic diagram that shows overall time acceleratorarchitecture according to the invention;

FIG. 16 is a block schematic diagram that shows recovery of an equationnumber from feedback values according to the invention;

FIG. 17 is a block schematic diagram that shows configuration ofrandomizer feedback according to the invention;

FIG. 18 is a block schematic diagram that shows captured packetclassification according to the invention;

FIG. 19 is a block schematic diagram that shows captured packetclassification for a parallel interface according to the invention; and

FIG. 20 is a block schematic diagram that shows a sample 4-bit feedbackshift register.

DETAILED DESCRIPTION OF THE INVENTION

The herein disclosed system is used for ultra-high speed classificationof data that have been organized into a serial or parallel data streams.The presently preferred embodiment of the invention provides a systemthat operates in the receive path, where electronic data are provided bythe optical interface to a data framer. In one embodiment, the inventionincorporates unique features into a traditional optical data framer chipand relies on a complex ASIC to permit the user to differentiate betweenup to 10,000 different patterns at light speed. One purpose of thegeneral purpose system disclosed herein is to eliminate the need forcostly and power consumptive content addressable memory systems, orcustomer pattern specific ASICs, to perform network packetclassification. The system operates on a principle of adaptiveprogrammable randomization to permit a differentiation between the inputvectors to be made. The invention dramatically reduces the processingburden required by high-speed optical routers or switches.

The modified data framer that is used in the preferred system is alsoreferred to as the novel data framer; the complex ASIC that is used tocontrol the adaptive programmable randomizer is also referred to as theASIC, both of which are discussed in greater detail below.

The herein disclosed optical network packet classification systemanalyzes the packet headers of messages sent over the Internet. At theirlowest possible level, these packet headers are made up of a sequence ofbits that are either a 1 or a 0. The address and networking informationfor each Internet packet are encoded into these header bits. Dependingupon the method of sending the packet, it is possible for there to bemany hundreds of bits in the packet header. These bits of data aretransferred through optical fibers by pulsing light on or off.

For discussion purposes, the Table D below shows how a packet headerwould look if it were broken into discrete bits. In this example, thepacket header is made up of only ten bits. The first bit to be sentusing a light pulse is B0, and the last bit to be sent is B9. Thesequence of light pulses corresponding to this packet header is1110101001.

TABLE D Sample 10 bit Packet Header (Example only) Bit B0 B1 B2 B3 B4 B5B6 B7 B8 B9 Value 1 1 1 0 1 0 1 0 0 1System Specifications

The following specifications (Table E) apply to a system comprising thepresently preferred embodiment of the invention. The generalspecifications apply to the overall system performance. The bit maskingspecifications apply to the ability to mask, or ignore, bits in thereceived packet header. In the case of the herein disclosed system,there is extensive flexibility for masking bits in one operation andthen removing the masking in a later step. The masking operation iscomparable to looking at a piece of mail and first checking only the zipcode to which it is being sent. The next step with the piece of mailmight be to look at the city and the street address to determine whichmail carrier should be given the letter.

TABLE E System Specifications Specification Group Specification NameSpecification General Maximum Number of Inputs 10,000 (Note 1) MaximumInput Length 1024 bits Maximum Classifiable Bits 10,240,000 bits AverageInput >50 Million Packets/sec Classification Rate (excluding (Note 2]Flexible Masking). Maximum Input Classification <50 nsec (Note 3] Timeper Masking step. Bit Masking Types of Bit Fixed Block and FlexibleMasking Provided Fixed Block Masking Length Permits gating off one blockof data bits that ranges from 1 to 1023 bits in length. Flexible MaskingBits 128 individually programmed bits in four selectable 32 bit blocks.Number of Flexible Masking 8 patterns that encompass Patterns permittedall 128 individually programmed masking bits. Maximum number of 8 stepsthat include sequential either a final flexible masking steps datapattern or one of the per input verification. flexible masking patterns.System novel custom ASIC Heart of the system for Components analyzingreceived data and determining the input. Novel data Framer Standard dataFramer product with modifications to support the System classificationprotocol. SRAM and DRAM Size based upon the number of inputs SRAM = 7nsec–15 nsec Access DRAM = 50 nsec Access Note 1 - The initial systemchipset is designed to handle 10,000 inputs. Architecturally, this couldbe increased to 40,000 inputs in a second version of the part.Ultimately, the architecture permits 80,000, 160,000, or more inputswith increased memory and ASIC sizes, but with no speed degradation. Theprogrammable masking patterns of the system permit significantly morethan 10,000 inputs to be handled effectively by the system. The 10,000input number refers to the number of either inputs or mask patterns thatcan be stored. Note 2 - Expected values through the use of 7 nsec SRAMsin the system and based upon an average of 2.35 SRAM accesses perclassification. Note 3 - Expected values through the use of 7 nsec SRAMsin the system and based upon a maximum of 6 SRAM accesses perclassification.

The number of fixed block masking periods and the number of flexiblemasking bits can be increased with increased ASIC sizes. The fixed blockmasking is intended for a long sequence of bits that are always ignored,while the flexible masking bits are provided to deal with individualfields of bits.

Example of Fixed Block Masking

Table F shows a setup where the length of the packet header to beevaluated is 564 bits. This value is called the input length. All bitsthat are received after the 564^(th) bit are not used in the packetclassification because they exceed the Input Length. A fixed blockmasking period from bits 136–227 is used in the example. This means thatbits falling within this bit window are not used in the inputclassification evaluation. As an example, the fixed block masking iscomparable to ignoring the sender's address when trying to determinewhere mail should be sent.

TABLE F Fixed Block Masking Bit Number Bits 0–135 Bits 136–227 Bits227–563 Bits 564–1023 Sample Bits Used in Bits not Used Bits Used inBits not Used due Header Evaluation due to Fixed Evaluation to exceedingBlock Masking Input LengthExample of Flexible Masking (Blocks)

Table G shows a setup where two, of a possible four, 32 bit flexiblemasking blocks are enabled. These blocks can be setup to fall on anyvalid 32 bit boundaries after the start of the header. In the example,the first flexible masking block #1 is setup to range from bits 96–127,which lies on a 32 bit boundary. The second flexible masking block #2 issetup to range from bits 352–383, which again lies on a 32-bit boundary.As an example, flexible masking is comparable to ignoring thedestination city and street selectively for the recipient of a piece ofmail in a rough check, and then looking at these only if the letter wassent using Next Day Air delivery.

TABLE G Example of 2 Flexible Masking Blocks Bit Number Bits 0–95 Bits96–127 Bits 128–351 Bits 352–383 Bits 384–703 Bits 704–1023 Sample BitsUsed Flexible Bits Used Flexible Bits Used Bits not Used Header inMasking in Masking in due to Evaluation Block #1 Evaluation Block #2Evaluation exceeding Input LengthExample of Flexible Masking (sub-Block)

Table H below shows bits 96–101 from flexible masking block #1 in TableG above. These five bits are shown to illustrate how the system permitsbit level masking flexibility for any bit in a flexible masking block.To account for different possible masking configurations based upon thenetwork protocols, addresses or fields that are received in the header,the presently preferred embodiment of the system provides eightselective masking patterns for each flexible masking block. The eightselective masking patterns are illustrated in Table H. In the case ofselective masking pattern #1, bits 96, 98, 99, and 100 are masked (=1),while bits 97 and 101 are not masked (=0).

TABLE H Selective Masking Patterns for Flexible Masking Bits (sub-Block)Bit 96 Bit 97 Bit 98 Bit 99 Bit 100 Bit 101 Selective 1 0 1 1 1 0Masking Pattern #1 Selective 0 0 0 1 1 1 Masking Pattern #2 . . .Selective 1 1 1 1 1 0 Masking Pattern #8System Benefits

The system provides a range of performance, cost, power, and sizebenefits. The following are some of the key benefits provided by theherein disclosed system:

-   -   Extremely Fast and Flexible Packet Classification—The system        exceeds the speed of content addressable memory systems in        packet processing. It permits extremely deep processing of bits        in the packet header without impacting classification speed.        When compared to custom solutions, the system provides deeper        and more flexible processing at comparable throughputs.    -   Unparalleled Search Latency—The system starts classifying a        packet immediately after the last bit has been received. There        is no overhead in performing data transfers to memory or to        custom ASICs. This opens up new optical routing and switch        architectures for ultra high performance.    -   Low System Power Consumption—After the initialization process,        the system has much lower power consumption than CAM or ASIC        alternatives.    -   Flexible and Programmable Masking—The system provides both fixed        block and flexible masking. The flexible masking can be        pre-programmed to go through sequential operations without        external intervention. This feature is a significant advantage        vis-à-vis content addressable memory approaches.        System Theoretical Background

The system uses a technique of adaptive, programmable, predictive, andsequential randomization to permit extremely rapid differentiationbetween a limited number of serial data bits. Optical networking relieson high speed transmission of digital data packets in a serial format.Optical routers and switches require that these serial packets beanalyzed to determine the appropriate source and destination of the datapacket so that they can be properly forwarded and at the correctpriority level. All known present systems of packet analysis requireserial data packets to be translated into a parallel format and thenanalyzed through the help of a combination of network processors,content addressable memories, custom ASICs, and high speed memories.

The randomization in the ASIC portion of the herein disclosed system isperformed using compact, programmable feedback shift registers that aredriven by the serial data stream. A general description as to how theseprogrammable feedback shift registers are used in the system is providedbelow. The final state of these shift registers is used as an index intoa memory array to determine which if any input data pattern has beenmatched. These shift registers require a simple register with exclusiveOR feedback taps that can be programmed to be enabled or disabled. Theyhave been designed to minimize power consumption, and the feedback tapenabling or disabling does not have an affect on the propagation delayof the feedback mechanism. The feedback mechanism has been kept simple,and minimal in terms of gate delays, to permit operation at extremelyhigh serial data rates. More importantly, the various programmablefeedback paths that are possible in the herein disclosed architecturehave been selected specifically to guarantee that output values from onefeedback value are uncorrelated to output values from another feedbackvalue. This uncorrelated feature permits general probability theory tobe used to evaluate the randomization of the data.

The predictive nature of the randomization comes from the fact that therandomization is pre-calculated for each possible input data pattern.This pre-calculation is done at the time that a new input data patternis entered into the system for use. A critical feature of the system isthat it implements a full hardware calculation of expected randomizationoutputs for each input that is applied. This hardware implementationallows many randomizer feedback values to be evaluated in real-time whena new input is applied. These randomizer output values are stored inmemory for each randomizer feedback that is being considered at thetime.

The adaptive randomization results from the system adjusting therandomization, over time, to handle the changing input data patternsthat are to be analyzed in the best fashion. The high speed predictivenature of the system permits a significant number of possiblerandomization feedback paths to be maintained in memory at any time. Thesystem can adjust the possible randomization feedback value after anypacket has been received. This is done if the existing feedbackrandomization is significantly less ideal than another feedbackrandomization that has been evaluated. The system maintains statisticson all presently evaluated feedback randomization to determine the bestrandomization, as well as any randomization that may be no longerusable. When a randomization is no longer usable, the system can quicklybring all of the input data patterns back to evaluate other possiblerandomization patterns.

The sequential randomization that is permitted in the system resultsfrom the ability for the user to implement sequential masking operationson the input data. The system permits fixed or programmable masking ofselected bit patterns within an input serial data stream. The maskingoperations of the system permit the user to pre-program a series ofmasking decisions that can result in a final input data pattern match.

Theoretical Randomization Probabilities

Detailed probability analysis is critical to an understanding of thesystem. The success of having a usable feedback randomization pattern,for a random set of inputs, depends upon the effective mapping of theinput data patterns to output vectors by the randomizer. For practicalimplementations, with significant numbers of input vectors andreasonable sized memories, a system must be able to handle a limitednumber of cases where two or more input data patterns are mapped to thesame output value. In the presently preferred embodiment of the systemthis is handled through a variety of methods including permitting a setvalue of multiple output cases where two, three, or four input datapatterns map to the same output pattern. In addition, a secondaryrandomizer is used to separate between the multiple outputs so that theappropriate input can be determined.

The detailed theory behind evaluating any given randomizer pattern ispresented below. This theory has been done in terms of the number ofpossible output states that are generated by the randomizer, and thenumber of possible input vectors that are being differentiated. Thelength of the input data patterns affects the predictive evaluation ofthe randomization outputs in hardware by the system, but it does nothave a first order affect on the randomization probabilities. One partof the discussion below develops the theory to show the odds that arandomizer produces a specific case of a certain number of non-pairedoutputs, paired outputs, tripled outputs, or quadrupled outputs for acertain number of input data patterns. Another part of the discussionbelow evaluates how permitting various numbers of multiple outputsaffects the possibility that a certain randomizer feedback is usable.For purpose of this discussion, unusable randomizer feedback occur whentoo many input data patterns map to the same output, or when as a group,there are too many sets of input data patterns that map to different butcommon outputs. As an example, if 4000 input data patterns mapped to2000 different outputs where there were two input data patterns for eachoutput, and the system permitted only 1000 multiple outputs, therandomizer feedback is unusable.

Primary Randomizer Feedback Selection Probabilities

The primary randomizer in the system is used to perform the mapping ofeach input data pattern to an output value. Given a number of input datapatterns, there are always certain randomizer feedback values that areunusable. The system has been designed to make sure that enoughrandomizer feedback are simultaneously evaluated so that a usablefeedback is always available. For purposes of evaluation, the systemevaluates the number of paired, tripled, and quadrupled output vectorsin determining which randomizer feedback to use, as well as to determinewhen a randomizer feedback should be discarded.

For a given number of output states, a given number of input datapatterns, and a given number of multiple outputs, it is possible todetermine the probability that any specific randomizer feedback maps theinput data patterns into a usable set of output states. The analysisbelow uses a total of 10000 input data patterns, 65536 (2^16) possibleoutput states, and 1024 (2^10) possible multiple outputs. For thisscenario, it can be calculated that any possible randomizer feedback hasan 95% chance of producing a usable mapping of the input data patterns.By using a set of eight possible randomizer feedback, the odds of havinga usuable mapping are 99.9999999961%.

The presently preferred embodiment of the system can use a total of 128(2^7) possible randomizer feedback. When one or more of the eightrandomizer feedback whose mapping has been evaluated becomes unusable,the system can use one of the remaining (128−8)=120 randomizer feedback.It should be noted, that from a practical standpoint, new feedback pathscan be swapped in while the input data patterns are loaded into thesystem.

Secondary Randomizer Feedback Selection Probabilities

The secondary randomizer differentiates between input data patterns thathave been mapped to the same output value. The calculations for the oddsof having a usable secondary randomizer feedback value are shown below.The probability analysis for this operation is much different than forthe primary randomizer because, in this case, it is only necessary to besure that the entries in each multiple are different from each other.

Randomizer Scaling for Additional Inputs

If the user wants to support additional inputs using the system, it ispossible to scale up the size of the randomizers to achievefunctionality. If the number of inputs were scaled to 40,000 input datapatterns, the number of outputs could be increased to 262,144 outputs,and the number of multiple outputs could be increased to 4096. Thiswould require an increase in the length of the primary and secondaryrandomizers to 18 bits in length. In addition, the memory requirementsfor storing the randomizer feedback mappings would increase by a factorof four.

System Overview

The primary method of operation for the system is used for ultra-highspeed packet classification of optical data that has been framed into aserial data stream. This method of operation is referred to herein asthe serial mode of classification. The invention provides packetclassification at the serial data stream level, as opposed to doing thisafter data has been put into a parallel format and transferred into anetwork processor system. This feature of the invention allows thesystem to produce extremely fast characterization in a predictabletimeframe that exceed anything done in a traditional parallel form suchas the example previously shown of a CAM based system. The serial modeof classification requires modifications to a standard data framer partin addition to the other components that make up the system.

A secondary method of operation for the system provides fast packetclassification of data packets that have already been stored in memoryas successive parallel words of data. This method of operation isreferred to herein as the parallel mode of classification. The purposeof this method of operation is to provide a legacy mode of operationthat can support on or more ports that may or may not have modified dataframers supporting the system. A design in which all ports have modifieddata framers supporting the system does not require use of the parallelmode of classification.

For the primary mode of operation, the system incorporates uniquefeatures into a traditional optical data framer chip, and relies on acomplex ASIC to permit the user to differentiate between thousands ofdifferent patterns at light speed. One reason for the general purposesystem is to eliminate the need for costly and power consumptive contentaddressable memory systems, or customer pattern specific ASICs, toperform network packet classification. The system operates on aprinciple of adaptive programmable randomization to permit thedifferentiation between the input vectors to be made. The system candramatically reduce the processing burden required by high-speed opticalrouters or switches.

FIG. 2 a is a block schematic diagram that shows an optical router orswitch 11 using the system. The modified data framer 22 that is used inthe system is referred to as the novel data framer. The complex ASIC 25that is used to control the adaptive programmable randomizer is referredto as the custom ASIC. In addition to these two parts, the system relieson a standard high speed SRAM 26 for internal processing, as well as alow speed DRAM 27 to store input patterns and other user values.

FIG. 2 b is a block schematic diagram that shows an optical router orswitch using the system in which the parallel mode of classification isused.

The presently preferred implementation of the herein disclosedarchitecture supports identification of up to 10,000 distinct inputvectors that can be up to 1024 bits in length. Both the number ofvectors and length of each vector can be modified should the situationrequire. Increasing the number of vectors beyond 10,000 would requireincreasing the length of the programmable randomizers and the width ofthe SRAM memory used by the custom ASIC. Increasing the length of theinputs results in a fairly linear increase in the overall size of thecustom ASIC and would require slight modifications to the data framerASIC.

Novel Data Framer

The novel data framer modifications are made to the serial data streamof a standard data framer chip. If a descrambling function is done, itis important that the data framer modifications be done after thedescrambling function. The serial data stream must be the same as theparallel data that is going to be passed to the network processor. It isalso important that the data framer be able to access the data frameroutputs that byte align the start of the packet, as well as count thenumber of bytes received.

FIG. 3 is a block diagram that shows the novel data framer. Themodifications to a standard data framer start with a primary andsecondary randomizer, 31, 32 respectively, that are programmablyconfigured by the custom ASIC. The PRIMFB[14:0] and SECFB[14:0]registers in the data framer are used to setup the feedbackconfigurations for the randomizers, and it is important that they bemodified only after the reception of a packet has been completed. Thesetwo randomizers are preferably compact circuits that operate at the fullserial data rate. They should preferably operate at 40 Gbit/sec serialdata rates and beyond.

The next change to a standard data framer part involves the addition ofa randomizer enable control block 33. The clock to the primary andsecondary randomizers are gated ON and OFF by the enable randomizersignal that is generated by this block. The enable randomizer signal isturned on at the start of a packet.

An optional implementation allows the data to the randomizers to beprogrammably turned OFF (Set to a 0) and then turned ON again to allowblanking out a portion of every packet received. This is done with thegate randomizer signal. The implementation shown in FIG. 3 allows asingle block of bits to be blanked out, but this could be extended tomultiple blanking periods should the application warrant this change.Finally, the enable randomizer signal is turned OFF after a userprescribed number of bits has been received. The system has beennominally designed to handle up to 1024 bits, but with modifications tothe custom ASIC and the data framer it could be easily extended to alarger number of bits should the application warrant.

The optional masking control block 34 in the data framer allowsprogrammable, sequential, user controlled masking of groups of userdefined bits. The implementation that is shown allows four different32-bit wide blocks of data to be captured for masking purposes. The useris able to configure with MASK0_START[4:0] to MASK3_START[4:0] fourstarting locations for 32-bit words to be sampled. The masking controlblock takes these four START values, in addition to the BIT_COUNT[9:0]register which is a count of the number of bits from the start of thepacket, to determine when to sample the MASKING data.

The PAR_DATA[31:0] is parallel data from the serial to parallelconverter 35 which is implemented within any data framer. ThisPAR_DATA[31:0] is sampled at the appropriate times to generateMASK0DATA[31:0] to MASK3DATA[31:0] which are four 32-bit wide maskingregisters that are associated with the packet, and can be read by thecustom ASIC when they become available. The number of MASK registers canbe modified with changes to the data framer as well as the custom ASICshould an application warrant this being done.

The output register synchronization and queue 36 assures that theprimary randomizer, secondary randomizer, feedback registers, andMASKING registers are stored for each packet. If a queue of packets isimplemented in the data framer, then these registers must be similarlyqueued so that they are associated with the appropriate data packets.Ideally, these registers should be available to the custom ASIC as soonas the number of bits identified by the STOP register are received, sothat they can be used to determine the appropriate input pattern match.

Primary and Secondary Randomizers

The primary and secondary randomizers are two equivalent circuits, andare designed so that their physical layout can be done so as to minimizegate propagation delays and hence to permit extremely fast operatingspeeds. These randomizers are expected to easily operate at 10Gbits/sec, and as technology improves in the coming years, the step upto 40 Gbit/sec should be possible.

The randomizers for the system are sixteen bits in length. They areconstructed using sixteen stages of D Flip/Flops in a serial shiftregister as shown in FIGS. 8 a and 8 b. The clocking of the serial shiftregister is qualified, and is done to all stages simultaneously. TheClock is gated with an Enable signal during the time periods between thestart and end of a packet where a bit is to be clocked into therandomizers. During periods within the packet reception where the MASKON/OFF functions is to be performed, the Clock to the randomizers isgated off. During periods within the packet reception where programmablemask bits are being captured, the Clock to the randomizers remains gatedon.

A global Clear signal is also applied to the randomizers. This signal isused to initialize the randomizers to a known all 0's state betweenpacket receptions. The Clear signal is not time critical so long as itis applied after the randomizer values have been latched, and prior tothe start of reception of the next data packet.

The feedback for the randomizers is structured as an XOR tree thatpotentially sums up all sixteen of the serial shift register bits andadds them to the Input data bit. For the case of a 16-bit randomizer,this translates to five levels of exclusive-or logic. The randomizerfeedback are turned on and off with the PRIMFB[14:0] and SECFB[14:0]registers. The last shift register bit is always applied to the feedbacknetwork, and hence the reason that there are only fifteen feedbackselection bits. Each feedback bit is used to gate the output of itscorresponding serial shift register stage using a two input AND gate.The PRIMFB[14:0] and SECFB[14:0] registers should only be written tobetween receptions of data packets. Changing these values does notaffect the actual primary randomizer or secondary randomizer outputs ifit is done while the randomizer clocks are gated off.

Enable and ON/OFF Circuitry

A key addition to a standard data framer is the generation of an Enablesignal for the primary and secondary randomizers. At a minimum, thissignal should enable the randomizers when a packet reception begins, andshould disable the randomizers when a specified number of bits have beenreceived. The optional ON/OFF circuitry in the custom ASIC handlesgating off large blocks of data that are not desired to be analyzed,occurring in the middle of data fields the user wants to analyze withthe system. This could consist of cyclic redundancy checks or otherfixed blocks of data in the received packet that are not pertinent tothe packet classification process. The purpose of the ON/OFF circuitryis to provide greater flexibility for use of the variable MASKING bits.

FIG. 9 shows a block diagram for the Enable and ON/OFF circuitry. Anenable state machine 90 is driven by inputs to turn the Enable signal ONor OFF. At the start of a packet, the Start of Packet signal fromexisting data framer circuitry is expected to go active, and the BitCount is expected to be 0. This forces the Enable signal ON at thebeginning of the packet. In a minimal configuration, when the Bit Countreaches the STOP value, the enable state machine turns the Enable signalOFF. A 10-bit comparator 91 is used to compare the status of the BitCount value to the value stored in the STOP register 92, and when thesetwo signals are equal, the END_EVAL signal is generated, followed by theEnable signal being turned OFF.

In the optional case where ON/OFF circuitry is implemented, additionalregisters and comparators are required. For each long blanking periodthat is desired, an additional two 10-bit registers 93, 94 are needed tostore the ON and OFF bit periods. In addition, two 10-bit comparators95, 96 are required to compare these ON and OFF values to the actual bitcount. The outputs of all of the comparators drive the enable statemachine. To increase the number of ON/OFF periods that are blankedrequires additional logic and power consumption. The enable circuitrycomparators are operating at the full clock rate of the system becausethey are driven by the bit count value.

Programmable Masking Circuitry

The ability to execute programmable masking in the data framer isentirely optional. In the world of content addressable memories, thisfeature is akin to a ternary CAM having three levels, i.e. one, zero,and don't care. The programmable masking circuitry permits blocks ofdata to be captured so that they can be programmably masked in the finaloutput result. To reduce power consumption and chip area, theprogrammable mask registers have been defined to be on even 32-bitboundaries, and to be 32 bits in length. The size, boundary, and lengthof these registers could all be adjusted based on user requirements. Theprogrammable masking circuitry performs a function similar to a logicanalyzer, by capturing blocks of data at the appropriate time, and thenpermitting them to be analyzed in the future in the custom ASIC.

In the implementation shown in FIG. 10, there are four masking startregisters labeled: Mask_Start0 100, Mask_Start1 101, Mask_Start2 102,and Mask_Start3 (not shown). Because the total possible length of thedata pattern being evaluated is 1024 bits, and the Mask_Start registersare intended to be on 32-bit boundaries, there are a total of 32possible values for each mask start register. These 32 values can bestored in a 5-bit number, and hence the Mask_Start registers are 5-bitvalues. This reduces the comparison with the previously mentioned BitCount register to only the upper five bits. The lower five bits of theBit Count register are compared with 0 because the value must be on a32-bit boundary.

The masking data are captured in a set of 32-bit registers labeledMASKDATA0 103, MASKDATA1 104, MASKDATA2 105, and MASKDATA3 (not shown).These registers are clocked when the Bit Count equals the value storedin the respective Mask_Start register. The data input to the MASKDATAregisters is from the serial to parallel data converter that exists in astandard data framer part. Once masking data are captured, they must beread from the output registers prior to the next packet being received.

Output Register Synchronization and Queue

It is critical that the primary and secondary randomizer values besynchronized to the feedback values that were used in determining them(see FIG. 11). The other registers in the system including theMask_Start, ON/OFF, etc. are not expected to be changed afterinitialization. If this is desired, then these need to be captured andstored with the primary and secondary randomizer values, and thereceived packet, so that they are correlated. It is the responsibilityof the data framer to keep the randomizer values and associated feedbackvalues with the correct received packets.

Custom ASIC Implementation

FIG. 4 is a block schematic diagram that shows the custom ASIC. Thecustom ASIC contains the intelligence, algorithms, and adaptivefunctionality for the system. The custom ASIC is responsible formaintaining multiple input pattern mappings associated with differentprimary and secondary randomizer equations. It determines the bestrandomizer selection, and decides when to switch randomizer values. Thecustom ASIC must also determine when a randomizer value is no longeruseful, and an entirely new mapping should be generated.

The preferred embodiment of the custom ASIC has four primary interfacesto the outside world, i.e. the microprocessor interface 41 is used tocommunicate to a host processor system, the DRAM interface 42 is used tocommunicate with either a standalone DRAM or shared dual port DRAM forstoring data patterns to be matched, the SRAM interface 43 is used tocommunicate with a dedicated SRAM that contains mappings for variousprimary and secondary randomizer settings, and the interface 44 is usedto communicate with the modified data framer part. Internally, thecustom ASIC handles mapping user inputs into values that are stored inSRAM. Individual masking and mapping optimization functions areperformed internal to the ASIC.

The following discussion views the custom ASIC from a data flowperspective:

For the custom ASIC to start it's process, the user is required to makevarious pointer and register configurations (see below). Next, the usermust load input patterns into the custom ASIC. These patterns are madeup of a combination of data and, in some cases, masking steps thatshould be done on the data in a potentially sequential fashion. Forinstance, the custom ASIC permits mapping a range of data values to asingle mask step output, and when that mask step output is reached,additional programmable masking or verification can be executed. Inputpatterns are handled by the input manager control and state machinesfunction 45 where they are directed into the input register 46. They arealso loaded into external DRAM for use in cases where an equationmapping is discarded, and a new mapping must be generated from scratch.The input register is 1024 bits long to permit patterns up to 1024 bitsto be analyzed. This length could be adjusted up or down in embodiments,and would not affect the data framer ASIC. Input data are manipulated in32-bit words, and masking is permitted for 32-bit lengths on 32-bit wordboundaries. Masking information is stored in conjunction with the inputdata so that an entire input pattern can be regenerated should newequation mappings need to be generated.

When the 1024 bit input register contains a complete data pattern, andwhen all masking information is loaded in the masking and enabling logicsection 47, it is possible to use the 1024 equation mapper 48 togenerate a related randomizer value. The masking and enabling logic 47is responsible for enabling only those input register bits that the useris interested in examining. For instance, if the user is interested inreviewing only the first 200 bits of an incoming data packet, the last824 bits are blanked out by the masking and enabling logic, and are notsent into the primary and secondary randomizers in the data framer. Themasking function of the masking and enabling logic allows data bitswithin the input pattern to always be masked out and not analyzed, aswell as permits bits to be masked selectively in a user programmablesequence.

The equation mapper 48 permits a randomizer value to be calculated in asingle cycle. This is done by implementing the mapper in pure logicgates in hardware. It calculates randomizer mappings for 128 differentequations simultaneously to permit extremely fast calculations and datastorage of randomizer values generated by different randomizerequations. This feature permits the custom ASIC to adjust adaptively toselect optimal randomizer settings based on the input and maskingpatterns that have been applied to the part. It allows many randomizermappings to be stored at one time without adversely affecting the setuptime for the part, and makes the action of generating entirely newmappings possible in the case where some of the mappings stored on thecustom ASIC are no longer usable due to excessive randomizer outputduplication.

The mapper multiplexer 49 is implemented in hardware to allow immediateselection between each of the possible 128 randomizer outputs associatedwith each of the 128 possible randomizer equations. This functionpreferably consists of sixteen individual 128:1 multiplexers, wherethere is a multiplexer associated with each of the sixteen output bitsof the randomizer. If the length of the randomizer is increased, thesize of this multiplexer increases in a linear fashion with the numberof bits in the randomizer output. The number of equations used in theequation mapper and the mapper multiplexer can be adjusted up or downwith a direct impact on the number of gates used in theirimplementation.

The mapper storage control and storage state machine 54 is responsiblefor saving and retrieving values from the various equation mappingtables. The state machines in this block handle determining whether thepresent location pointed to by a primary randomizer value contains 0, 1,2, 3, or 4 entries. This state machine is responsible for handling thecreation and destruction of multiple entries, and the adjustment of themultiple entry tables that dictate those entries that are used. Thisfunction works directly with the external SRAM in storing and retrievingthese values. This function works closely with the masking engine,especially in those cases where mask steps are involved.

The masking engine 51 handles all aspects of permitting the user tosetup sequential masking operations. This function takes user inputsthat setup which, if any, 32-bit blocks of data are operated on in amasking fashion. The user is permitted to signify data bits as alwaysbeing masked, or as selectively being masked when certain circumstancesarise. Once the masking engine knows what bits may be masked, it isresponsible for calculating the effect of each bit on the output vector.These effects are referred to as masking impact bits. To execute thisoperation, the masking engine injects a single “1” into the input vectorstream at each bits location. The output primary randomizer value showsthe impact of this input on the output vector. This value is then usedby the masking engine, along with the masking data that is received fromthe data framer ASIC, to remove the effects of the masked data when apacket is received. The masking functions used in the system aredescribed in greater detail below.

The time accelerator 52 is responsible for re-mapping a receivedrandomizer value to generate the randomizer value that would have beenreceived if zero values had been clocked into the randomizer for a fixednumber of cycles after the received randomizer value was captured. Thisfunction is described below, and permits a flexible and fast way to skipforward to the end of the 1024 input bits that are always used tocalculate randomizer values. As an example, if the user wishes toanalyze only 200 bits of data, while the novel custom ASIC alwayscalculates using an input vector length of 1024 bits, the timeaccelerator block generates the effect of having 824 trailing 0'sshifted into the randomizer after the data of interest. This methodreduces time latency, and permits the randomizers to be turned off muchsooner to reduce power consumption.

The mapper engine, statistics and state machine 50 is responsible fordetermining the equations to be used by the system, and to determinewhen equations are no longer usable and need to be replaced. Thisfunction maintains statistics on all equation mappings that aremaintained in memory. Using these statistics, it selects the bestmapping and sends it to the data framer ASIC.

The master control block 53 is responsible for initializing the entiresystem at startup. It also handles communicating with other controlblocks to execute system wide functions such as a hard reset.

SRAM Memory

Dedicated SRAM is required for the custom ASIC. The size of the SRAMmemory is dictated by the size of the primary randomizer/secondaryrandomizer words, and the number of equations that are permitted. Thespeed of the SRAM is critical because it sets the performance of thesystem. As an example, a 16-bit primary randomizer value, in conjunctionwith a 16 bit secondary randomizer value, dictates that the core of theprimary randomizer lookup table be 2*2^16=131,072 entries long andsixteen bits wide. In addition, a multiple entry table of 1024 entriescontains slightly more than 8,096 locations that are sixteen bits wide.In this example, it takes a total of approximately 140,000×16 bits ofSRAM storage per equation. A 512K×16 SRAM handles approximately threeand one-half equations worth of data.

DRAM Memory

A dual port DRAM could be used for the DRAM required in the system. Thelowest cost configuration is a synchronous DRAM. The fact that thecustom ASIC is the only device talking to the DRAM, unless a dual portapproach is used, permits a purely synchronous approach to be simplyimplemented. The speed of the DRAM memory directly impacts how fast newinput vectors can be stored in the system. The microprocessor interfaceto the ASIC is a 32-bit interface. If the DRAM is sixteen bits wide,then it's interface must be twice as fast. Burst operation is verycritical because an entire input could be stored away at one time.

System Benefits

Fastest Packet Processing Possible.

As soon as the last serial data bit that is under analysis has beenreceived, the system's primary randomizer, secondary randomizer andmasking bit values are available from the data framer ASIC. These wordscan be read into the custom ASIC using high speed parallel 32 bittransfers (taking<5 nsec). Once these data are transferred to the novelcustom ASIC, the time to match a pattern is a function of threevariables, i.e. the number of masking operations that the user wants toperform, the speed of the SRAM used by the custom ASIC, and thedistribution of multiple outputs within the search that is performed.

Multiple outputs are distributed in a probabilistic fashion throughoutthe search process. The odds described below assume that there are up to968 paired outputs, up to 50 tripled outputs, and up to six quadrupledoutputs within a 10000 input data pattern space. In this scenario, theodds of a pair are less than 2*968/10000=19.4%, the odds of a triple areless than 3*50/10000=1.5%, and the odds of a quadruple are less than4*6/10000=0.24%. These are extremely conservative bounds because, in theexample, all of the probability distribution is for cases that are lessthan or equal to the 968 pair, 50 triple, and six quadruple scenario.When a pair, triple, or quadruple output is hit, the system uses thesecondary randomizer value to differentiate between the different inputdata patterns.

The speed of the SRAM used by the custom ASIC dictates the timeassociated with sequential SRAM access to determine the appropriateinput data pattern. In addition, each sequential masking step, excludinga fixed masking of bits which does not entail SRAM cycle overhead,results in an additional search through SRAM memory.

The search time for a pairs, triples, and quadruples is shown in TablesI–L below. Each of these tables lists the average and maximum time tocomplete a search.

TABLE I Time associated with Searching a Single Match SRAM Search StepAction Probability of Step 1 Read primary randomizer Value 1.0 (ContainsInput) 2 Check secondary randomizer Value 1.0 Average Search Steps 2.0Maximum Search Steps 2.0

TABLE J Time associated with Searching a Pair Match SRAM Search StepAction Probability of Step 1 Read primary randomizer Value 1.0 (Containspointer to Multiple Structure) 2 Check First secondary randomizer 1.0Value in the Multiple Structure 3 Check Second secondary 0.5 randomizerValue in the Multiple Structure 4 Read the input number for the 1.0correct secondary randomizer Value in the Multiple structure. AverageSearch Steps 3.5 Maximum Search Steps 4.0

TABLE K Time associated with Searching a Triple Match SRAM Search StepAction Probability of Step 1 Read primary randomizer Value 1.0 (Containspointer to Multiple Structure) 2 Check First secondary randomizer 1.0Value in the Multiple Structure 3 Check Second secondary 0.67 randomizerValue in the Multiple Structure 4 Check Third secondary randomizer 0.33Value in the Multiple Structure 5 Read the input number for the 1.0correct secondary randomizer Value in the Pair structure. Average SearchSteps 4.0 Maximum Search Steps 5.0

TABLE L Time associated with Searching a quadruple Match SRAM SearchStep Action Probability of Step 1 Read primary randomizer Value 1.0(Contains pointer to Multiple Structure) 2 Check First secondaryrandomizer 1.0 Value in the Multiple Structure 3 Check Second secondary0.75 randomizer Value in the Multiple Structure 4 Check Third secondaryrandomizer 0.50 Value in the Multiple Structure 5 Check Fourth secondaryrandomizer 0.25 Value in the Multiple Structure 6 Read the input numberfor the 1.0 correct secondary randomizer Value in the Pair structure.Average Search Steps 4.5 Maximum Search Steps 6.0

In calculating the average search steps per mask step, the previousprobabilities for multiple outputs can be used.

The SRAM speed, could be increased to improve the overall search time.The flexible masking steps are an additional feature that requireadditional searches in CAM solutions. It should be remembered that thereis no additional overhead for a fixed masking of data bits. The searchtime provided by this embodiment of the invention is approximately fivetimes faster than comparable CAM implementations, and is on par with thesearch time of a hardwired ASIC2 approach by Juniper Networks. Thehighlights with this approach are that it is extremely deep in it'ssearch, it is flexible in terms of allowing multiple masking operations,and it has the lowest latency of any solution.

Lowest Possible Search Latency

The system has the lowest possible packet search latency that ispresently known. This occurs due to the fact that the system operates ona serial data stream prior to any parallel operations of transferringthe data into memory. Alternative CAM or ASIC based systems musttransfer all appropriate data bytes from a data framer into either aprocessor memory or directly into a CAM or ASIC solution for evaluation.The time required to perform this function adds latency to the packetthrough either a router or switch product. Reducing this latency helpsguarantee that higher level protocols do not time out as packets arerouted over an entire link.

The system can produce a guaranteed upper bound on the time required toevaluate a received packet after the packet is received. Thisdeterministic delay could be useful in an alternative system whereoptical routing is performed using a detection system and an opticaldelay line.

FIG. 5 is a block schematic diagram that shows an embodiment of theinvention in which an optical delay line 51 is used to make a decisionas to where to route a packet prior to the packet arriving at the end ofthe delay line. Using this capability, an optical switch 52 directs thedata into the correct path without having to store and regenerate theoptical signal.

The optical router architecture shown in FIG. 5 has some clearadvantages and limitations. Light traveling down the optical delay linetakes longer than the combination of the system's packet search time andthe time to have the optical switch actually switch and settle out. Thenetwork processor is much simpler because it's basic function is toconfigure the system, and to set the selection signals for the alloptical switch. If the system could guarantee a packet routing decisionin 50 nsec, and the all optical switch could switch and settle in 50nsec, then the optical delay line would have to be 100 nsec long. Thiswould entail using over 100 feet of optical fiber within the router foreach input that was to be sampled.

In addition to the physical challenges of the delay line, the signalprotocol issues would have to be developed. All optical switches beingdeveloped today setup a connection and leave it there for a long periodof time. This means that their switching time is not critical, and theconnection is bi-directional.

Lower System Power Consumption

Power consumption is a critical parameter on line cards and in othernetworking gear. Reducing power consumption can have a ripple effect onoverall system costs, and can also provide more degrees of freedom forthe board and system designer. The system has been designed to take themost processing intensive burden away from the network processor. Thispermits designers to react by reducing clock speeds or decreasing memorybandwidths and achieve equivalent performance. Either of these choicesreduces power consumption and cost.

The system has been designed for minimal power consumption. The dataframer primary and secondary randomizers operate at full clock speeds,but are only driven during the portion of a receive data packet that isbeing evaluated. The design of these randomizers minimizes their powerconsumption. The remainder of the data framer consists of configurationor sampling registers that are read or written only once per packet, andhence draw very little power.

As with the data framer, the custom ASIC has also been designed forminimum power consumption. The custom ASIC and associated memory systemare very active during configuration and draw higher power levels atthat time. Once configuration is complete, the custom ASIC is fairlystatic. It executes SRAM cycles when primary and secondary randomizerwords are read from the data framer, but these are limited in duration.Otherwise, the custom ASIC operates with little dynamic powerconsumption. In contrast to the system, both a prior art custom ASIC anda CAM system require extensive power consumption while they are active.

Flexible and Programmable Masking on the Fly.

Typical CAM based search engines permit global masking and bit specificmasking of any bit in the data pattern. Generally, there are a limitednumber of bit patterns where this capability is required. The flexibleand pre-programmable masking sequences that the system permits, offloadadditional processing work from the network processor. Based on the typeof packet being received, the system can process the packet withdifferent sequential masking operations.

Using the System on a Router Backbone

In the interest of cost savings, the system permits multiple dataframers to be operated from a single custom ASIC. Many systems, such asthe Juniper ASIC2 and prior art CAM based systems, can operate with thepacket classification processing done on a network router backbone asopposed to on each channel. In the system, each input channel requires adata framer ASIC, but a performance tradeoff allows a single custom ASICto be used for N data framers.

FIG. 6 is a block schematic diagram that shows the system on a routerbackbone 60. The use of the system in the router backbone configurationdoes not have the latency improvement benefits of the implementation oneach optical channel. In this configuration the system competes withlarge CAM based processing systems, and with Juniper Networks ASIC2solution. The system is faster than the CAM based alternatives, and isat least as fast as the ASIC2 solution. It is also possible to usemultiple custom ASICs to increase aggregate processing power in terms ofpackets/second.

In terms of implementation, the data framer interfaces are preferablyall in parallel so that a single custom ASIC 25 a could write to eachdata framer 22 at once. This entails setting up the randomizer feedbackvalues. The randomizer outputs, masking registers, and feedback valuesused to analyze each packet are added on to each received packet. Thesepackets are sent through each network processor 61 onto the routerbackbone. On the router backbone, a main router processor 62 isresponsible for queuing the packets, stripping the data off and routingit into the custom ASIC, and using the custom ASIC outputs to determinehow to route the packet.

Unsynchronized Data Pattern Extraction Capability

The architecture of the system provides a unique opportunity to performultra-high speed searching for many unsynchronized data patterns in astream of high speed serial data. By the term unsynchronized datapattern, what is meant is a data pattern where the start of the patternis not known, and the pattern is embedded in a stream of data. In thecase of searching a data stream for specific text or other patterns, thesystem allows up to 10000 patterns of up to 1024 bits to be searchedsimultaneously in a rapid fashion. In the future of genetic research, ifit was possible to take a sample of genetic information, and break itdown into it's sequences while doing this in a brute force fashion onall chromosomes simultaneously, the following based approach wouldpermit all of the genetic data to be scanned rapidly for matches with upto 10000 genetic sequences. In this way, an extremely rapid analysis ofa genetic fingerprint for an individual could be made. Each base in aDNA strand can be represented with two bits of data, so the ASIC couldfind strands that are up to 512 bases in length. The length could beincreased beyond 512 bases with a simple redesign to the novel customASIC.

The system for scanning random data for a match can be implemented usingmultiple novel style circuits as shown in FIG. 7. The total number ofnovel circuits 22 a is equal to the number of bits that are to beanalyzed in the receive data stream. An additional N bit counter 71 isused for two purposes, i.e. to generate a “Start of Pattern” signal, andto be used to select the appropriate novel circuitry output using amultiplexer 72. The “Start of Pattern” signal is shifted in one clockcycle increments so that each novel circuit begins checking the patternat a position 1 bit shifted from the previous novel circuit. This offsetmeans that regardless of where the start of the actual data pattern liesin the receive data stream, one of the novel circuits starts the primaryand secondary randomizers on the first bit of the data pattern.

The single bit offset between novel data framers also means that one ofthe data framers produces an output each bit period. The n:1 multiplexerroutes the correct data framer output to the novel custom ASIC 25 duringeach bit period. During this time, the primary and secondary randomizeroutputs and any masking outputs must be transferred into the novelcustom ASIC and used there. The serial speed of this system is limitedby the search time of the system. The current worst case pattern matchtakes six SRAM cycles for the case of a quadruple output match. Using aworst case of 50 nsec for a match, the serial data rate can be up to 20Mbits/sec if only fixed masking operations are used. A serial data rateof 20 Mbits/sec allows the data framer ASIC circuitry to be implementedeasily in silicon.

One issue that affects the asynchronous data stream much more than theoptical networking situation is the case of false detection. If sixteenbit primary and secondary randomizers are used, there is a one in 65,536chance that a valid primary randomizer number has random data generate amatching secondary randomizer value. There are a variety of ways inwhich this can be handled. A first method is to check the data always tomake sure that it was a match; a second method is to increase the sizeof the memory and hence reduce the odds of both valid primary andsecondary values; and a third method is to use an offset pattern checkto make sure that two successive readings point to the same value. Theoffset pattern check can be used if less than ¼ of the possible datapatterns are being searched. In this case, the length of the searchpattern can be increased by one bit. Every desired pattern is prependedby 0, prepended by 1, appended by 0, and appended by 1 to generate fournew patterns that are each one bit longer than the desired pattern. Whenthe system receives a match for a specific data pattern, there mustalways be a match for the very same specific data pattern on the verynext bit period. If this does not occur, there was a false detection.This approach decreases the odds of a false detection by a factor offour billion (2^16)2^.

Another issue that could arise in searching the genome is the fact thatinput data patterns are of various lengths based on the gene. Thisrequires there to be additional masking registers to permit a wide rangein data lengths. As an example, if strands of 26, 52, 64, 78, 84, 100,160, 220, and 330 bits in length were to be checked, the masking wouldhave to be done sequentially, and would reduce the overall throughput.All strands would be verified for the first 26 bits, and the resultwould direct towards measuring the next (52−26)=26 bits for all casesthat were not the 26 bit strand. At that point, the (52−26)=26 bitswould be verified, and the result would direct towards measuring thenext (64−52)=12 bits for those cases that were not the 52 bit strand.This would extend on until all the steps were taken.

Normally, if ten masking steps were used, the throughput of the systemwould be reduced by a factor of ten, but the throughput reduction couldbe greatly minimized through a variety of methods. In the case ofgenetic pattern matching, the frequency of cases where more than onemask step would be taken is extremely small, and usually would occuronly if a valid pattern was correctly bit aligned. As a result, thesystem must handle extremely rare cases where multiple masking steps maybe taken. This could be done efficiently by using a FIFO (first in firstout) buffer in front of the novel custom ASIC to buffer the incomingrandomizer values to handle the multiple masking cases, or by shuttingoff the serial data clock until a check has been completed. Theimportant criteria here is that the most efficient searches occur whenall of the data patterns to be checked are of the same length.

The novel data system opens up exciting opportunities in the arena ofdata mining and pattern matching. Table M identifies the time that thissort of an asynchronous data pattern detection system would take tosearch through the entire Human Genome. Printed text is not a goodexample of an asynchronous data stream because it is already framed atthe character level, and can be easily translated to be framed at theword and/or sentence level.

TABLE M Asynchronous data Search Times using Novel System Item SearchTime Notes Entire Human Genome 300 seconds This is a futuristic conceptwith no marker framing (5 Minutes) that relies on base pair (3 Billionbase pairs) sequencing without regard to markers. Each Base Pair is 2bits of information, and all elements being searched are the samelength.Features of the SystemHighly Specialized Programmable randomizer in a Serial Data Path

The programmable randomizer in the system is unique in a number of waysranging from the method of programmability, the random nature of it'soutputs, the simplicity of making predictive calculations as to it'svalue over a long stream of inputs, and the ease of predicting theaffects of any specific input on the output state to effect rapidmasking calculations.

Linear feedback shift registers have been used for decades in a varietyof applications including cyclical redundancy check generators (CRCs),pseudo random bit sequence generators (PRBSs), and data scramblers. Inmost of the known applications, the feedback taps on these shiftregisters are selected at the point of design to maximize theirrandomization features. The pseudo random bit sequence generator anddata scrambler applications use a linear feedback shift register toproduce a serial data pattern that is as random as possible. Thecyclical redundancy check generators operate on a serial data stream,and produce a parallel word at the completion of reception that is usedto verify that the correct data stream has been received. In thisrespect, the system's use of a linear feedback shift register is similarto the application of a cyclical redundancy check generator.

The system differs dramatically from a CRC generator in the respect thatit has programmable taps that allow 2^(n−1) different programmablefeedback to be selected instead of a single fixed feedback. The “n−1”term arises because the final “nth” stage of the shift register mustalways be fedback in the preferred implementation. Further, the feedbackare setup to exclusively-or the serial data with any combination of(n−1) shift register stages. The exclusive-or feedback allows a fixedtree of exclusive or gates to be used to exclusively-or all of theselected feedback outputs. Each output is gated with an “and” gate tocontrol programmably whether or not it is used by the exclusive-or tree.A key feature of this approach is that it is extremely compact and easyto program. This dramatically reduces die size and power consumptionbecause the circuitry is meant to operate at extremely high serial datarates, and the more logic that is toggling at these data rates, the morepower that is consumed.

A purpose of the randomizers is to differentiate between input datapatterns, and not to provide the most random possible pattern. What ismore critical, is that each input affects outputs differently whenswitching between various feedback mechanisms. This orthogonalitybetween how different outputs are impacted by each input, through arange of equation feedback, permits general random probability theory tobe used in calculating output distributions.

The design and choice of the randomizer is critical to the ability topredict quickly in hardware the mapping from an input data stream to anoutput randomizer value. The sole use of exclusive-or gates in thefeedback mechanism, as opposed to other forms of logic such as “AND,”“NAND,” “OR,” or “NOR” gates greatly simplifies the predictive abilityin hardware. In addition, the use of exclusive-or gates makes itpossible to single out each individual input, and identify it's effecton each bit of the output pattern. This feature is critical forpermitting simple masking to be performed. Finally, this approach iscritical to permitting variable length packets to be easily analyzed.This is possible by the fact that any bit that is beyond the length ofdata to be evaluated, can be forced to a 0 in the analysis hardwaretree, and the bit is effectively eliminated.

Single Cycle Hardware Calculation of Randomizer Values

The system operates on the ability to pick the best feedback mechanismfor mapping input data patterns into output vectors in a rapid fashion.This requires that the system must be able to calculate output vectorsin an extremely rapid fashion for a number of feedback selections. Thesystem uses a hardware tree of exclusive-or gates to calculate outputvectors for a large number of feedback selections (nominally 1000feedback selections) in a single clock cycle. This is possible toimplement by analyzing the effects of each and every input bit on theoutput pattern using a computer program in advance. Once these computermappings are performed, they can be merged together for all of thepossible feedback so that as many logic gates as possible are re-used.Finally, an output multiplexer allows the appropriate output vector tobe selected for the feedback mechanism that is being evaluated.

Randomizer Gating Implementation

The primary and secondary randomizers in the system are gated on and offfor three specific reasons, i.e. at the initiation of reception of adata packet they are turned on, at the completion of the reception ofthe data bits of interest they are turned off, and during any period inwhich the user always desires to blank out analysis of a sequence ofdata bits they are turned off and then back on at the end of thesequence. This ON/OFF gating of the randomizers, through userprogrammable control, is a unique feature to the system. This ON/OFFgating capability works in tandem with the single cycle hardwarecalculation of randomizers circuitry, where data bits during any “OFF”period are forced to a “0” from the perspective of randomizercalculations.

Programmable Masking Architecture

In CAM or ASIC implementations of packet classification systems, databits can be masked off by essentially not considering them in a bit bybit comparison. The masking capability in the system is very unique.Instead of the traditional approach of blanking out or ignoring a databit to mask it, the system calculates the effect of each data bit thatthe user desires to mask on the randomizer outputs, captures the actualmasked data bits, and then effectively subtracts the masked data bitsout of the randomizer output result using specialized hardware. The dataframer incorporates the circuitry to capture the masked data bits, andthe custom ASIC incorporates extensive circuitry to calculate theeffects of each masked data bit on the output predictively, as well asthe circuitry to subtract out the effects of the masked data bits.

Sequential Masking Capability

In addition to the ability to mask out data bits in a received packetstream, the system allows the user to setup programmed sequentialmasking of data bits where initial pattern matches can automaticallydrive subsequent masking operations without user intervention during theprocessing of the randomizer outputs. This sequential masking capabilityis normally done through processor intervention based on the outputs ofvarious decisions. The system permits this decision driven masking to besetup proactively in advance of a packets reception. This reduces theoverhead required of a network processor, and reduces the latency inmaking a routing decision.

Adaptive Randomizer Feedback Analysis and Selection

The architecture revolves around the ability to develop and maintaininformation regarding a number of randomizer feedback at any giveninstant in time, and to pick the best randomizer feedback adaptivelyusing established criteria. The custom ASIC manages the memory (SRAM)tables associated with each feedback selections mappings. In addition,counters for the number of pairs, triples, quadruples, and overflowoutput vectors are maintained in hardware. These counters are used toidentify the randomizer feedback that is least likely to need to bechanged, as well as any randomizer feedback that are no longer viable.The evaluation and swapping of randomizer feedback is a real time andadaptive process based on the latest information as to the input datapatterns being evaluated.

Input Manager Control and State Machines

In the preferred system, the user is allowed to provide up to 10000different inputs that are up to 1024 bits long. This memory is a maximumof 10,240,000 bits of storage. The system returns a pointer to the datainput that matches the incoming data stream. Therefore, the user shouldstore the data in sequential locations. A single valid bit for eachinput is used to signify that the input data pattern is valid and shouldbe used by the system. The external memory system is specified as using32-bit wide memory. Therefore, it requires 32 memory accesses to read amaximum length data input. The user can write an input, and thenactivate that input by writing to it's associated valid bit.

External Memory Input Data and Input Valid Structures

The purpose of the external DRAM memory storage is to store input datapatterns and masking information for potential future needs. If certainrandomizer feedback must be eliminated due to excessive multiplestructures or multiple structure overflows, it is necessary for thesystem to read all of the input data patterns back into the system frommemory so that new patterns can be evaluated. Another reason for storingthe input data is to permit users to read back any input data patternthat is being used in the custom ASIC system to evaluate the pattern, orto modify it to create another input data pattern.

The user can define the location in the external memory where the customASIC stores the input table. This table is called the INPUT_DATA array,and it's starting location is pointed to by the 32-bit pointerINPUT_DATA_BASE that is located on the custom ASIC. Thirty-two bits ofwidth allows for an addressable memory size of 4.29 G.

The user must define the number of bits of data that each input datapattern contain, and this value is stored in INPUT_DATA_LENGTH that islocated on the custom ASIC. This value can be in one bit increments, butfrom a storage perspective, input data patterns are stored in 32-bitwords. Any data bits beyond this length value are masked out. In thecase of an exclusive-or function, this is done by masking the input to a0. For the custom ASIC, the maximum valid value is 1024 bits. Inembodiments this value could be extended in length.

In addition to the input data pattern, the system must know what maskingis required for the specified input. This information is referred to asthe present masking step. Any bits in the pattern that are masked areignored from the perspective of the stored input data pattern. If amasking step is performed after the present input data pattern withoptional masking is evaluated, the next masking step must be specified.These two masking steps are stored after all of the input data patterndata words and are associated with the specific input data pattern (seeTable N below).

TABLE N Storage of Input data Pattern and Mask Step Information (SingleINPUT_DATA entry) Bits 31:24 Bits 23:16 Bits 15:8 Bits 7:0 Data Word 0Input Data Input Data Input Data Input Data Pattern[31:24]Pattern[23:16] Pattern[15:8] Pattern[7:0] Data Word 1 Input Data InputData Input Data Input Data Pattern[63:56] Pattern[55:48] Pattern[47:40]Pattern[39:32] . . . . . . . . . . . . . . . Data Word n Input DataInput Data Input Data Input Data Pattern Pattern Pattern Pattern[(n*32)+31: [(n*32)+23: [(n*32)+15: [(n*32)+7: (n*32)+24)] (n*32)+16](n*32)+8] (n*32)] Masking X X Next Mask Step Present Mask Step Word

The user must also signify which inputs are valid. This is done with theINPUT_VALID array, where a single bit is used to signify the validity ofeach user input. To conserve on data, this array is a 10000×1 bit arraythat can be accessed in 32-bit reads/writes. The first 32-bit locationin the array signifies the status of inputs 0–31. The second 32 bitlocation in the array signifies the status of inputs 32–63, etc . . .Coverage of 10,000 Input data patterns requires a total of 313 32-bitwords. The INPUT_VALID_BASE is used to indicate the location of thearray that contains the valid status for each input location (see TableO below).

TABLE O Storage of Input Valid Information (Entire INPUT_VALID array)Bits 31:24 Bits 23:16 Bits 15:8 Bits 7:0 Input Valid Input Valid [31:24]Input Valid [23:16] Input Valid Input Valid Word 0 [15:8] [7:0] InputValid Input Valid [63:56] Input Valid [55:48] Input Valid [47:40] InputValid [39:32] Word 1 . . . . . . . . . . . . . . . Input ValidWord 312

Input Valid[(n*32) + 15:(n*32) + 8] Input Valid[(n*32) + 7:(n*32) + 8]

The shaded area includes valid entries for Inputs 10,000 to 10,015 whichare unspecified.

The INPUT_DATA and INPUT_VALID information is all stored in externalDRAM memory. Table P below describes the location of these arrays.

TABLE P External Memory Input Structures (Entire DRAM Storage) LengthName (in 32 Bit Words) Starting Location Notes INPUT_VALID    313INPUT_VALID_BASE Each bit in this array signifies the validity of aninput data pattern. Initialized as all zeros. INPUT_DATA 330,000(maximum) INPUT_DATA_BASE The Maximum size per  20,000 input datapattern is 33 × 32 (minimum) bit words (1024 bits of Input data plus oneMasking Word). The actual size will depend upon the INPUT_LENGTH. Thisarray requires no initialization.Registers Associated with Input Data Structures

The following registers are located on the custom ASIC, and are used towrite and clear user input data patterns located in the externalINPUT_DATA array. In addition, they are used to modify the INPUT_VALIDarray appropriately. The INPUT_DATA_BASE and INPUT_VALID_BASE registersstore the base addresses of the external structures as described herein,and the INPUT_DATA_LENGTH register stores the length of each input aspreviously described. The INPUT_DATA_WORD_COUNT is used as a counter topoint to the individual words in the INPUT_DATA array. This value isautomatically incremented after each word is written to, or read from,the INPUT_DATA array. The INPUT_DATA_NUMBER refers to the input datalocation that is being operated on, and falls in the range of 0 to9,999. This location must be written to prior to operating on theINPUT_DATA array, and is stored in the USER_INPUT_DATA_NUMBER location.The INPUT_AUTO_LOCATION register is used by the system to identify thenext available user input that has not been setup as valid. If the userwishes to use this input for the next Input data Pattern, the valueshould be read, and then written into the USER_INPUT_DATA_NUMBERregister.

Within the input manager control and state machine, the necessaryinformation regarding masking regards the masking required for thedescribed input, and whether the randomizer results drive an additionalmask step, or whether they are a final result. A later section onmasking describes in detail how the masking is handled and calculated.The PRESENT_MASK_STEP value stores the masking step to be used on thepresent data inputs. Any bits that are covered by this masking operationare disregarded with respect to their storage in the INPUT_DATA array.The NEXT_MASK_STEP value dictates whether there is an additional maskingstep. A NEXT_MASK_STEP value of 0 indicates that this is a final value,and when reached, the user receives the INPUT_NUMBER for thecorresponding INPUT_DATA pattern that has been matched. The two MASKregisters are stored automatically by the system after all of the inputdata words have been loaded into DRAM.

In addition to the aforementioned registers, there are a group ofregisters within the input manager control and state machines (see TableQ below) that are used for internal operations. INPUT_STRUCT_PTR is ageneral purpose pointer used to manipulate data. INPUT_STRUCT_VALUE is ageneral purpose register used to store either INPUT_DATA or INPUT_VALIDinformation. INPUT_VALID_ENCODE is used to store the result of a 32 to 1priority encoder, and the INPUT_CONTROL_REG is described below.

TABLE Q Storage Associated with User Inputs Address Name Size R/WDefault Notes 0x00 INPUT_VALID_BASE 32 R/W   0 Points to the Bits firstentry in the INPUT_VALID data structure. 0x01 INPUT_DATA_BASE 32 R/W 313 Points to the Bits first entry in the INPUT_DATA Structure. 0x02INPUT_DATA_LENGTH 10 R/W 1023 This is the Bits length in bits of theuser input data pattern that is to be evaluated. 0x03INPUT_DATA_WORD_COUNT  5 R/W X This register Bits stores the word countwithin the input data pattern. 0x04 USER_INPUT_DATA_NUMBER 16 R/W X Thisis the Bits number of the input data pattern that is being operated on.It is used for both writing and clearing input data patterns.SYS_INPUT_DATA_NUMBER 16 X This is the Bits number of an input datapattern that the system wishes to operate on. It is used when checkingthe validity of inputs, or loading inputs from the system.INPUT_NUM_SOURCE_SEL  1 Bit X This selects the user writtenUSER_INPUT_DATA_(—) NUMBER when set to a 0, and the System selectedSYS_INPUT_DATA_NUMBER when set to a 1. The output of this register isreferred to as the INPUT_DATA_NUMBER. 0x05 INPUT_AUTO_LOCATION 16 R XThis is used Bits by the system when it determines the next availableinput to write. 0x06 PRESENT_MASK_STEP  4 R/W X This selects Bits theMasking that should be done on this Input Pattern. A value of 0indicates that this is not a masking step. 0x07 NEXT_MASK_STEP  4 R/W XThis dictates Bits whether an additional MASK step will be taken whenthis pattern is detected. A value of 0 indicates that this is a finalvalue. 0x08 INPUT_STRUCT_PTR 32 X X This is a Bits general purposeregister to be used as a pointer into either the INPUT_DATA orINPUT_VALID structures. 0x09 INPUT_STRUCT_VALUE 32 R/W X This is a Bitsgeneral purpose register to be used to store values to be read orwritten to the INPUT_DATA array, or to the INPUT_VALID array. 0x0AINPUT_VALID_ENCODE  5 X This is a Bits general purpose register to beused to hold the output of a 32 bit priority encoder used for theINPUT_VALID structure. 0x0B INPUT_CONTROL_REG  9 R/W X Control BitsRegister for Input data and Valid Manipulation. See detailedDescription.INPUT_CONTROL_REG Details

The INPUT_CONTROL_REG (see Table R below) contains all of the controlbits associated with modifications to the INPUT_DATA array and theINPUT_VALID array. These bits include those necessary to Initialize theINPUT_VALID array, to write new INPUT_DATA, and to read INPUT_DATA. Thespecial AUTO_LOCATION feature is used to permit the system to determinethe next available INPUT_DATA location. This is an option that ispermitted in cases where the user does not want to keep track of thisprocess in a tight fashion.

TABLE R INPUT_CONTROL_REG BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT2 BIT 1 BIT 0 Input I/O Ready Buffer Unused Inputs Wrap Command CommandValid Full Input Full Complete

-   -   BITS [2:0] The Command field is used to select an input data        pattern operation to perform. A command of 0 signifies that no        operation should be done, and is the steady state for this        register. A write of a non-zero value will start an operation,        and immediately clear the Command Complete bit. When an        operation has been totally completed, the Command Complete bit        will be set. An operation can only be terminated with a Reset        Command of all Ones. On Power-Up, the Command field will be set        to “001” to Initialize the Input Valid array. When the        Initialization sequence completes, the Command Complete bit is        set.        -   Code Command        -   “000” No-Operation        -   “001” Initialize Input Valid array        -   “010” Write/Load Input into DRAM        -   “011” Write Input into DRAM        -   “100” Read Input from DRAM        -   “101” Clear Input from DRAM        -   “110” Check Input Valid        -   “111” Reset Command    -   BIT 3 The Command Complete bit is set to a “1” when the        specified command has been completed. If the Command Complete        bit is a “0”, only the Reset Command can be written to the        Command field.    -   BIT 4 The Wrap Bit is used to signify that the system has        wrapped over the maximum value in the INPUT_VALID array. This is        used in the process of searching an unused input.    -   BIT 5 The Inputs Full Bit is used to signify that there are no        open inputs available in the structure.

BIT 6 The Unused Input bit is used to signify that the system hasidentified the next available input location, and the input number isstored in the INPUT_AUTO_LOCATION register.

-   -   BIT 7 The Buffer Full bit is used to indicate that either the        Write Buffer when setting up a pattern, or the Read Buffer when        reading back a pattern is full.    -   BIT 8 The I/O Ready bit is used to signify that the system is        ready for a write or a read operation that has been previously        setup.

BIT 9 The Input Valid bit is used to signify that an input being checkedis storing a valid input that is being used by the system.

Inputs and Equation Correlation

It is critical that there be correlation between the inputs that arestored and the ones that have been mapped by various equations. Asinputs are written or cleared, they are always calculated for all activeequations at that time. The equation update generator uses anEQUATION_INPUT_UPDATE_PTR to cycle through all of the valid inputs. If anew input is stored in the middle of this process, or an input iscleared, the EQUATION_INPUT_UPDATE can be temporarily discontinued toallow that to occur. When equation updates are being made, it isnecessary to initialize (clear) out the entire primary and secondaryrandomizer tables.

Processes Associated with Input Control

The processes shown in Table S below are used to manipulate the inputarray and the input valid databases.

TABLE S Processes Associated with Input Control Process/Macro NameProcess Type Description INIT_INPUT_VALID Internal Used to initializethe Input Valid Array. USER_CHECK_VALID External Used by the user todetermine whether a specific Input Number is Valid and being used by theequation Mappers. SYS_CHECK_VALID Internal Used by the system todetermine whether a specific Input Number is Valid and being used by theequation Mappers. SYS_GET_AVAIL_INPUT Internal Used to determine thenext available input location in the user input array.USER_INPUT_WR_LOAD External Used to write a user input into DRAM forstorage, and loads it into the Input Register. USER_INPUT_WRITE ExternalUsed to write a user input into DRAM for storage. This procedure doesnot load the input register. USER_INPUT_READ External Used to read auser input from DRAM. This procedure does not load the input register.USER_INPUT_CLEAR External Used to clear out a user input from DRAM. Thisprocess automatically involves loading it into the Input Register.SYS_INPUT_LOAD Internal Used to read a user input from DRAM and load itinto the Input Register without having the user read the value. Thisprocess is used for internal equation table regeneration.Input Register Arbitration and DRAM Access Arbitration

There are five processes that require access to the DRAM. Two of theseprocesses, USER_INPUT_WR_LOAD, and USER_INPUT_CLEAR, also load the inputregister. The user should be accessing only one of the threeuser/external processes at a time because it is the user'sresponsibility to finish one action prior to starting another. From theperspective of the 1024-bit input register, there are three processesthat result in it being loaded: USER_INPUT_WR_LOAD, USER_INPUT_CLEAR andSYS_INPUT_LOAD. The SYS_INPUT_LOAD and USER_SYS_INPUT_VALID procedurescan be initiated by the system, as part of a full equation swap, and areless critical than an immediate change by the user with either theUSER_INPUT_WR_LOAD or the USER_INPUT_CLEAR processes (see Table Tbelow).

TABLE T Input Register Arbitration Process Priority RationaleUSER_INPUT_WR_LOAD Highest When the user wishes to add a new input tothe system, this should take the highest priority. USER_INPUT_CLEARMedium Clearing an input is less critical than writing a new input intothe system. SYS_INPUT_LOAD Lowest This routine is called when refreshingan equation which should take the lowest priority.

The DRAM memory can be accessed by a number of processes describedabove. It is necessary to have arbitration between these processes, sothat any two do not conflict over the use of internal registers. Theweights in the Table U below are meant to show how often one of thefollowing actions should be taken when two actions are being requested.The real issue here is the relative weights. For example, aUSER_INPUT_WR_LOAD occurs eight times for every USER_INPUT_LOAD if bothare continually being requested.

TABLE U DRAM Access Arbitration Priority And Arbitration Process WeightRationale INPUT_VALID_INIT 10/10 Must be done on initialization prior toany other operation on the user data. USER_INPUT_WR_LOAD  8/10 Highpriority since new user writes are more critical than reads or clears.USER_INPUT_WRITE  2/10 Lower priority since this write is not beingpresently used or mapped. USER_INPUT_READ  5/10 Read may be needed tocalculate a new value to write into the chip. GET_AVAIL_INPUT  4/10 Maybe critical for a new write to occur. SYS_INPUT_LOAD  2/10 Used by thesystem for equation updates. USER_INPUT_LOAD  1/10 Should rarely takepriority over user activities.Inter-Block Communication

It is necessary for the mapper engine, statistics, and equation statemachine to be able to read input data values from DRAM into the inputregisters so that they can be mapped and stored. This is important forthe equation update process.

The I/O ready bit in the input control register is used to hold-off reador writes to the custom ASIC until the proper internal function has beencompleted. In addition, the I/O ready bit is used to handle the largerissue of holding off the user while the system uses the input registersto recalculate an equation. A round robin arbiter is used to make surethat the system and the user get alternating preference on occasionswhere a conflict exists. As the user issues a command, the systemdetermines whether the mapper engine, statistics, and equation statemachine is also requesting access. If the internal mapper . . . ” blockhas priority, the I/O ready bit is kept at a level until the internaloperation completes (see Table V below).

TABLE V Inter-Block Signals (Input Manager Control and State Machine <->mapper Engine, Statistics and equation state machine) Input ManagerSignal Direction Notes Request Input Signifies that the mapper Enginewishes Input Control to perform an operation Input Control Output Passescontrol of the Input Manager Acknowledge registers to the mapper EngineLoad Input Input Used by the mapper Engine to start a Register fetchfrom DRAM. The USER_INPUT_DATA_NUMBER must be previously loaded by thesystem. Input Register Output Tells the mapper Engine that the data inLoaded the Input Register is for a complete input.1024-Bit Input Registers

There are four sources of data that need to be able to drive theequation mapper, i.e. a new user input that should be mapped and storedfor future use, a previously stored user input that should be broughtback for analysis with a new equation, special bit patterns required forinput data masking analysis, and parallel data that is received andrequires packet classification. The discussion above described howarbitration between new user inputs and previously stored user inputs isperformed. Neither of these functions is time critical, but eitherrequires significant overhead in setup and should not be interruptedprior to completion. The special bit patterns required for input datamasking analysis are described herein, and they are independentlygenerated and multiplexed into the source of the equation mapper.Finally, parallel data that are received and require packetclassification have a time critical component. Due to the timecriticality for parallel classification, an independent set of registersis used to store this data. This permits decisions to be made rapidly,and results in minimal disruption to the new user input and previoususer input analysis that may be occurring concurrently.

1024-Bit Input Register for Analysis

There are 1024 input bits in the custom ASIC that store and operate onuser defined input data patterns. The INPUT_STRUCT_VALUE holdingregister routes to 32 different input data registers that are each 32bits in length. The select for each bank of registers is cycled throughfrom Bank0 to Bank31 as a total input vector is loaded into the customASIC. The input data registers are not externally readable or writeableby the user. The INPUT_DATA_WORD_COUNT register routes theINPUT_STRUCT_VALUE to the appropriate INPUT_REG_BANKn (see Table Wbelow).

TABLE W Input Register data Structure Name Size Notes INPUT_REG_BANK0 32Bits Contains Input data Pattern Bits[31:0] INPUT_REG_BANK1 32 BitsContains Input data Pattern Bits [63:32] INPUT_REG_BANK2 32 BitsContains Input data Pattern Bits [95:64] . . . INPUT_REG_BANK31 32 BitsContains Input data Pattern Bits [1023:991]

The user's access to input data patterns is through theINPUT_STRUCT_VALUE register. The user can indirectly load the inputregisters through writing a new input data pattern into the custom ASIC,by reading and modifying a value stored in DRAM, and by clearing a valuestored in memory. The system also is responsible for loading theseregisters during the operation of generating new randomizer values for anew equation. Table X below describes operations that result in loadingthe 1024-bit input register.

TABLE X Table of Operations that Load the 1024-Bit Input RegisterProcess Initiator Data Source USER_INPUT_WR_LOAD User INPUT_STRUCT_VALUE(Written by User) USER_INPUT_CLEAR User DRAM SYS_INPUT_LOAD System DRAM1024-Bit Input Register for Classification

There are 1024 input classification bits in the custom ASIC that analyzereceived data patterns for parallel classification. TheINPUT_CLASS_VALUE holding register routes to 32 different input dataregisters that are each 32 bits in length. The select for each bank ofregisters is cycled through from Bank0 to Bank31 as a total inputclassification pattern is loaded into the custom ASIC. The inputclassification registers are not externally readable or writeable by theuser. The INPUT_CLASS_WORD_COUNT register routes the INPUT_CLASS_VALUEto the appropriate INPUT_CLASS_REG_BANKn (see Tables X and Y below).

TABLE X Registers Associated with Parallel Input Classification NameSize Note INPUT_CLASS_VALUE 32 Bits Contains Input Classification bitsINPUT_CLASS_WORD_COUNT  5 Bits Selects one of 32 Input ClassificationRegisters to direct the INPUT_CLASS_VALUE to. Automatically incrementsafter write. When this exceeds the INPUT_DATA_LENGTH, it interrupts theMaster Controller so that a Parallel Classification will be performed.

TABLE Y Input Classification Register data Structure Name Size NotesINPUT_CLASS_REG_BANK0 32 Bits Contains Input Classification Bits[31:0]INPUT_CLASS_REG_BANK1 32 Bits Contains Input Classification Bits[63:32]INPUT_CLASS_REG_BANK2 32 Bits Contains Input Classification Bits[95:64]. . . INPUT_CLASS_REG_BANK31 32 Bits Contains Input ClassificationBits[1023:991]

The user's access to input classification patterns is through theINPUT_CLASS_VALUE register. The user directly loads the inputclassification registers through writing a new input data pattern intothe custom ASIC

Masking and Enabling Logic and Masking Engine Details

The masking and enabling logic and the masking engine in the custom ASIChandle all aspects of the programmable masking function. The first majorfunction is storage of user masking information including a descriptionof the input data bits that are to be masked, as well as informationidentifying what bits are to be masked at what step of the sequentialmasking process. The second major function is the circuitry to generatethe fixed masking of specified data bits. The third major function isthe mask impact calculation circuitry. This circuitry drives the inputdata to determine the effect of each data bit on the output vector, sothat when the bit is masked, it's effect can be cancelled out wheninterpreting a randomizer value. The fourth major function involvesinterpreting the outputs of the data framer to account for masking.

User Masking Information

The first level of masking information that must be stored by the systemis the masking of all data bits beyond the length of data that the userdesires to analyze, and the masking of data within a fixed OFF/ON periodafter the start of the input data pattern. To implement the length andOFF/ON period masking, a set of 1024 input enable bits is used to gatethe input data bits to a zero in the cases where the bit is to beignored. The INPUT_DATA_LENGTH register in the input section identifiesthe number of data bits that must be evaluated. The following registersidentify the bit range that is to be masked by the OFF/ON period, andthey are both user readable and writeable. The enable bits dictatewhether the register are used and it's value is sent to the data framer(see Table Z below).

TABLE Z Off/On Register Description Address Name B10 B9-B0 0x10MASK_OFF_CYCLE_REG Enable Mask Off Start Location 0x11 MASK_ON_CYCLE_REGEnable Mask On Start Location

The user is supplied with four 32-bit input blocks that can be used forfixed and/or programmable bit masking. To achieve the effect of forcedmasking for bits covered by each enabled Programmable Mask register, theuser must explicitly mask the bit pattern for each masking step patternthat is used. The 32 bit input blocks occur on 32-bit word boundaries,and can be described with simple five bit numbers (1024/32=32 or fivebits). These 5-bit values identify bits in the received data patternthat are captured by the data framer in it's masking registers. Inaddition, a sixth bit is used to identify whether the mask register isto be enabled or disabled. This impacts whether the data framer capturesthe corresponding data. Disabling unnecessary masking conserves overallsystem power consumption. All of the mask register enable bits are setto 0 at power-up so that masking is disabled. All of the mask registerstart registers are both user writeable and user readable (see Table AAbelow).

TABLE AA Programmable Mask Registers Address Name B5 B4 B3 B2 B1 B0 0x12MASK_REGISTER_0 Enable Mask Start Value 0 0x13 MASK_REGISTER_1 EnableMask Start Value 1 0x14 MASK_REGISTER_2 Enable Mask Start Value 2 0x15MASK_REGISTER_3 Enable Mask Start Value 3

The custom ASIC provides up to eight selective masking steps, andpermits the user to use any combination of these steps for a specificdata circumstance. Selective Mask Step 0 is always used as the initialmasking step when a packet is received. Selective Mask Steps 1–7 areused to handle occasions where the user wishes to mask subsets of databased upon specific packet types or parameters. Each of the 32×4=128maskable bits have eight selective masking bits associated with them fora total of 1024 selective masking step bits. All selective masking stepregisters are both user readable and user write-able. If a MASK_REGISTERis disabled, the selective step bits are ignored (see Table AB below).

TABLE AB Selective Masking Step Registers Address Name B31:B5 B4 B3 B2B1 B0 0x20 MASK_REG0_SMS0 Forced Masking bits for Mask Register 0 0x21MASK_REG0_SMS1 Masking Bits for Mask Register 0 with Selective MaskingStep 1. 0x22 MASK_REG0_SMS2 Masking Bits for Mask Register 0 withSelective Masking Step 2. 0x23 MASK_REG0_SMS3 Masking Bits for MaskRegister 0 with Selective Masking Step 3. 0x24 MASK_REG0_SMS4 MaskingBits for Mask Register 0 with Selective Masking Step 4. 0x25MASK_REG0_SMS5 Masking Bits for Mask Register 0 with Selective MaskingStep 5. 0x26 MASK_REG0_SMS6 Masking Bits for Mask Register 0 withSelective Masking Step 6. 0x27 MASK_REG0_SMS7 Masking Bits for MaskRegister 0 with Selective Masking Step 7. 0x28 MASK_REG1_SMS0 ForcedMasking bits for Mask Register 1 0x29 MASK_REG1_SMS1 Masking Bits forMask Register 1 with Selective Masking Step 1. 0x2A MASK_REG1_SMS2 . . .1 1 1 1 0 0x2B MASK_REG1_SMS3 . . . 0 1 0 1 0 0x2C MASK_REG1_SMS4 . . .1 1 1 0 1 0x2D MASK_REG1_SMS5 Masking Bits for Mask Register 1 withSelective Masking Step 5. 0x2E MASK_REG1_SMS6 Masking Bits for MaskRegister 1 with Selective Masking Step 6. 0x2F MASK_REG1_SMS7 MaskingBits for Mask Register 1 with Selective Masking Step 7. 0x30MASK_REG2_SMS0 Forced Masking bits for Mask Register 2 0x31MASK_REG2_SMS1 Masking Bits for Mask Register 2 with Selective MaskingStep 1. . . . . . . 0x3E MASK_REG3_SMS6 Masking Bits for Mask Register 3with Selective Masking Step 6. 0x3F MASK_REG3_SMS7 Masking Bits for MaskRegister 3 with Selective Masking Step 7.

In Table AB, the addresses 0x2A, 0x2B and 0x2C have been expanded forbits 0 to 4 for illustration purposes. In this example in selectivemasking pattern 2 for mask register 1, bits 1–4 are masked. In selectivemasking step 3 for mask register 1, bits 1 and 3 are masked. Inselective masking step 4 for mask register 1, bits 0 and 2–4 are masked.

Forced Masking Circuitry

The custom ASIC includes 1024 bits that are used to enable or disablethe bit from consideration. These bits are used to drive the selectionof whether an input data bit drives the mapper circuitry, or whether a“0” value is switched in to mask out the value (see table AC below). Allbits that are contained within the fields of enabled Programmable MaskRegisters will automatically be enabled for purposes of driving themapping circuitry.

TABLE AC Input Enable Registers Name Size Notes INPUT_ENAB_BANK0 32 BitsContains Enables for Input data Pattern Bits[31:0] INPUT_ENAB_BANK1 32Bits Contains Enables for Input data Pattern Bits[63:32]INPUT_ENAB_BANK2 32 Bits Contains Enables for Input data PatternBits[95:64] . . . INPUT_ENAB_BANK31 32 Bits Contains Enables for Inputdata Pattern Bits[1023:991]

Within the masking and enabling logic, there is a block ofinitialization circuitry that can load up the INPUT_ENAB_BANKnregisters. The steps of this initialization include: setting all of thebits to enabled, clearing out all enables after the INPUT_DATA_LENGTHvalue, and disabling bits that occur between the MASK_OFF_CYCLE_REG andthe MASK_ON_CYCLE_REG. The forced masking steps affect every input datapattern, and as such, it is expected that they are setup once uponinitialization. If any of these registers are changed, the entire customASIC and respective mappings become invalid, and require recalculation.The forced masking state machine is started after the appropriate usersetup sequence (see Table AD below).

TABLE AD Forced Masking State Machine Registers Name Size NotesSET_ENAB_BANK 5 Bits Counter to count through the 32 possible inputbanks SET_ENAB_BIT 5 Bits Counter to count through the 32 bit locationswithin an input bank. SET_ENAB_FROM_SMS0 1 Bit Signifies that there hasbeen a match with one of the four mask registers. SET_ENAB_SMS0_SELECT 2Bits Signifies the specific mask register that has been matched.FORCE_MASK_ON 1 Bit When this bit is set, bits will be Force Masked as aresult of a MASK ON/OFF function or exceeding the INPUT_DATA_LENGTH.WRITE_BIT 1 Bit This is a bit that is ready to write into theappropriate enable register.Mask Impact Calculation Circuitry

The masking impact of each bit that is in one of the four 32-bit maskingregisters must be calculated for each equation that is used. As a newequation is swapped in, theses bits must be calculated prior tore-evaluating all of the available inputs. Each input bit can affect anyof the sixteen output bits in the primary randomizer pattern. Therefore,there are a maximum of 16×4×32=2,048 bits that must be stored per eachequation. With a set of eight equations, this translates to a total of8×2048=16,384 masking impact bits. Because it is critical that themasking impact bits be available in real time for equation calculations,it is important that these mask impact registers be stored on the customASIC. The masking impact registers are internal, and are notuser-readable (see Table AE below).

TABLE AE Masking Impact Register Structure (Internal to custom ASIC)Name Description EQ0_MASK_REG0_IMP_BIT0 equation 0, Mask Register 0, Bit0–16 Bit mask impact EQ0_MASK_REG0_IMP_BIT1 equation 0, Mask Register 0,Bit 1–16 Bit mask impact . . . . . . EQ0_MASK_REG0_IMP_BIT31 equation 0,Mask Register 0, Bit 31–16 Bit mask impact EQ0_MASK_REG1_IMP_BIT0equation 0, Mask Register 1, Bit 0–16 Bit mask impactEQ0_MASK_REG1_IMP_BIT1 equation 0, Mask Register 1, Bit 1–16 Bit maskimpact . . . . . . EQ0_MASK_REG1_IMP_BIT31 equation 0, Mask Register 1,Bit 31–16 Bit mask impact EQ0_MASK_REG2_IMP_BIT0 equation 0, MaskRegister 2, Bit 0–16 Bit mask impact EQ0_MASK_REG2_IMP_BIT1 equation 0,Mask Register 2, Bit 1–16 Bit mask impact . . . . . .EQ0_MASK_REG2_IMP_BIT31 equation 0, Mask Register 2, Bit 31–16 Bit maskimpact EQ0_MASK_REG3_IMP_BIT0 equation 0, Mask Register 3, Bit 0–16 Bitmask impact EQ0_MASK_REG3_IMP_BIT1 equation 0, Mask Register 3, Bit 1–16Bit mask impact . . . . . . EQ0_MASK_REG3_IMP_BIT31 equation 0, MaskRegister 3, Bit 31–16 Bit mask impact EQ1_MASK_REG0_IMP_BIT0 equation 1,Mask Register 0, Bit 0–16 Bit mask impact EQ1_MASK_REG0_IMP_BIT1equation 1, Mask Register 0, Bit 1–16 Bit mask impact . . . . . .EQ1_MASK_REG0_IMP_BIT31 equation 1, Mask Register 0, Bit 31–16 Bit maskimpact . . . . . . . . . . . . EQ7_MASK_REG3_IMP_BIT0 equation 7, MaskRegister 3, Bit 0–16 Bit mask impact EQ7_MASK_REG3_IMP_BIT1 equation 7,Mask Register 3, Bit 1–16 Bit mask impact . . . . . .EQ7_MASK_REG3_IMP_BIT31 equation 7, Mask Register 3, Bit 31–16 Bit maskimpact

The calculation of the masking impact bits is done by injecting a single“1” pattern into every appropriate bit in the input data pattern. As aninput of a “1” in a specific masked bit is applied, the output of themapper circuit is a 16-bit mask impact that needs to be stored. Thismask impact can then be calculated for each of the eight activeequations before the walking “1”s pattern is advanced (see FIG. 12). Thewalking 1's pattern is generated by writing a 10-bit value into theWALKING_ONE_VALUE register, and having it drive a 10:1024 decoder. Theoutput of the decoder is a single “1” in the location identified by theWALKING_ONE_VALUE register.

The input source select directs whether the input register or thewalking one's pattern should be used to drive the mapping circuitry (seeTables AF and AG below).

TABLE AF Internal Register associated with Masking Impact CalculationRegister Size Notes WALKING_ONE_VALUE 10 bits Signifies the input thatis to be set to a “1” for Masking Impact test purposes.INPUT_SOURCE_SELECT  1 bit “1” selects the Input Register to drive themapping circuitry. “0” selects the Walking One's pattern to drive themapping Circuitry. INPUT_CLASS_SELECT  1 bit “1” selects parallel inputclassification mode. “0” selects the input register pattern used tocalculate mapping values. EQUATION_STORE_ENTRY  3 bits Signifies theequation being used. Valid equations range from 0 to 7.

TABLE AG Output Signals from the 10 bit decoder Decoder Output SignalsNotes WALKING_ONE_OUTPUT[1023:0] Routes to multiplexers associated witheach input data bit.

The walking ones pattern must be driven by the system into the inputsthat are associated with each MASK_REGISTER. A state machine sequencesthrough the registers to accomplish this task (see Table AH below).

TABLE AH Internal Signals driving the 1024 equation Mapper Signal SizeNotes MAPPER_SOURCE0[31:0] 32 Bits Signal Bits[31:0] that drive theMapper MAPPER_SOURCE1[31:0] 32 Bits Signal Bits[63:32] that drive theMapper . . . . . . . . . MAPPER_SOURCE31[31:0] 32 Bits SignalBits[1023:991] that drive the Mapper

The mapper outputs must be routed to the appropriate mask impactregisters for the equation that is being addressed. For instance, whenequation 1's mapping is being checked for MASK_REG0 and the system islooking at the impact of bit 31 in the register, the mapper value iswritten to the register EQ1_MASK_REG0_IMP_BIT31. The mapper outputs mustbe routed to a total of 1024=(8 equations*4 mask registers*32 bits) maskimpact registers. The novel custom ASIC must be able to generate anenable for each of these registers that is based on the equation number,the bit number, and the MASK_REGISTER.

Output Mask Adjustments

When a randomizer value from the data framer is received, the systemmust adjust it by canceling out any bits that have been masked. Thisoperation is done using the mask impact registers and effectively addingthe appropriate values into the received word based on the equationbeing used at the time. In the case of the primary and secondaryrandomizer values, different equations are used to generate thesenumbers (see Table AI below).

TABLE AI Randomizer Received Registers Address Name Size Notes 0x00PRIM_RANDOMIZER_RX 16 Bits Novel data framer ASIC primary randomizerreceived value 0x01 SEC_RANDOMIZER_RX 16 Bits Novel data framer ASICsecondary randomizer received value

The storage registers for the mask capture data from the data framer areused in the calculation to cancel out the effect of masked bits (seeTable AJ below).

TABLE AJ Mask Register Capture Data Address Name Size Notes 0x02MASK_CAPTURE_DATA_0 32 Bits Novel data framer ASIC Mask Capture data forMASK_REGISTER_0 0x03 MASK_CAPTURE_DATA_1 32 Bits Novel data framer ASICMask Capture data for MASK_REGISTER_1 0x04 MASK_CAPTURE_DATA_2 32 BitsNovel data framer ASIC Mask Capture data for MASK_REGISTER_2 0x05MASK_CAPTURE_DATA_3 32 Bits Novel data framer ASIC Mask Capture data forMASK_REGISTER_3Parallel Classification Output Mask Adjustments

When a parallel data pattern is loaded into the system from themicroprocessor interface for classification, the system must adjust itby canceling out any bits that have been masked. This operation is doneusing the mask impact registers and effectively adding the appropriatevalues into the received word based on the equation being used at thetime. In the case of the primary and secondary randomizer values,different equations are used to generate these numbers (see Table AKbelow).

TABLE AK Parallel Classification randomizer Registers Name Size NotesPRIM_RANDOMIZER_PAR 32 Bits This value is latched from the output of themapper Multiplexer. SEC_RANDOMIZER_PAR 32 Bits This value is latchedfrom the output of the mapper Multiplexer.

The storage registers for the mask capture data from the data framer areused in the calculation to cancel out the effect of masked bits (seeTable AL below).

TABLE AL Parallel Classification Mask Register Capture Data Name SizeNotes MASK_CAPTURE_PAR_0 32 Bits Mask Capture Register 0 for ParallelClassification mode. MASK_CAPTURE_PAR_1 32 Bits Mask Capture Register 1for Parallel Classification mode. MASK_CAPTURE_PAR_2 32 Bits MaskCapture Register 2 for Parallel Classification mode. MASK_CAPTURE_PAR_332 Bits Mask Capture Register 3 for Parallel Classification mode.Illustration of Programmable Masking

To determine the post masking result for any bit in a randomizerpattern, there are a total of four values that must be considered, i.e.the non-masked randomizer output (PRIM_RANDOMIZER_RX orSEC_RANDOMIZER_RX), the sequential mask step for the specific bit forthe specific equation being analyzed (MASK_REGm_SMSp_EQn), the maskimpact for the specific bit (EQn_MASK_REGm_IMP_BITq), and the actualcaptured status of the masked bit (MASK_CAPUTURE_DATA_m). From a maskingperspective, there are a total of 128 (32×4) bits that can be masked. Atthis point, the mask registers, the mask capture data registers, and themask impact registers are all relative, and we are not concerned withthe absolute location within the data word. What is important is whethera specific bit is being masked in a specific selective masking sequence,whether the bit impacts the output vector, and whether the bit wasactually captured as a one. Due to the nature of the randomizerimplementations, data bits that are 0 do not impact the output vector(see Table AM below).

TABLE AM Internal Register to choose the Selective Masking Step RegisterName Size Notes SELECTIVE_MASK_SELECT 3 Bits This register is written bythe system to choose the Selective Masking pattern to be used incalculations.

The programmable masking function can operate on either the primary orthe secondary randomizer value. The system must be able to switchbetween these between any two cycles because evaluation of the primaryand secondary values must be done in successive operations whensearching the database. The RANDOMIZER_SELECT register determines whichof these two randomizer values is analyzed.

The novel custom ASIC permits analysis of either data (serial) orparallel data passed over from the microprocessor. The SOURCE_SER_PARsignal is used to select between these two sources of data. This signalpermits the system to operate while receiving packet classificationinformation through these two possible interfaces (see Table AO below).

TABLE AO Internal Register to choose the randomizer Output to beanalyzed Name Size Notes RANDOMIZER_SELECT 1 Bit This register iswritten by the system to choose the randomizer to be analyzed by theMasking Analyzer. A “0” value selects the primary randomizer, while a“1” value selects the secondary randomizer value. SOURCE_SER_PAR 1 BitThis register selects between classifying data from the Serial interfaceor the Parallel Microprocessor interface. A value of “0” selects theNovel interface, and a value of “1” selects the Parallel Interface.

To illustrate the programmable masking function, consider one of thepossible 128 bits that can be masked (see FIG. 13). The use of buses inthis example signify that there are parallel implementations of thelogic for each of the data bits. The outputs for this bit must be sentthrough an exclusive-or tree to add them in with the remaining 127 maskbits and the initial randomizer value.

In this example, an XOR tree masks the 128 possible masked bits with theselected randomizer output. The system permits a sequential selectivemasking approach (see Table AP below). In a sequential masking approach,the output of the first masking must point to a location in memory.

The system allows the user to specify a sequence of masking steps thatcan be taken for a given data pattern. In other words, the primaryrandomizer output can be changed for bits 0–4 of one of the maskingwords in the first pass, and then bits 5–7 in the second pass. Themasking steps are provided in the primary randomizer table entries. Thecustom ASIC could be developed for expansion of the ability to logicanalyzer capture serial data in the event a simple change to the dataframer is made.

TABLE AP Sequential Masking Protocol Process Step Action Next ProcessStep Determination Initial primary Read the primary randomizer   1) Usethe Forced Masking primary randomizer value from the Novel Datarandomizer Output value to index into the Read Framer. primaryrandomizer Table. Mask Original primary 1.1) If this is a final entry,then verify the randomizer value with secondary randomizer value (ifSELECTIVE_MASK_STEP0 to configured to do so). If there is a generate aninitial selective valid match, then report the input to masking primaryrandomizer the user. Output. This is done internal to 1.2) If the entryis a Selective Masking the Novel 10K ASIC Entry, then progress to thespecified Selective Masking Level. Selective Mask Original primary 1)Use the latest Selective Masking primary Masking randomizer Pattern withthe randomizer Output value to index into the chosen Selective Maskingprimary randomizer Table. Pattern to generate a new 1.1) If this is afinal entry, then verify the Selective Masking primary secondaryrandomizer randomizer Output. This is value (if configured to do so). Ifdone internal to the Novel 10K there is a valid match, then report ASIC.the input to the user. 1.2) If the entry is a Selective Masking Entry,then progress to the specified Selective Masking Level.Processes Associated with the “Masking and Enabling Logic” Block

Table AQ below shows processes are used to setup the enable bits and tocalculate the masking Impacts for each selected bit.

TABLE AQ Processes Used to Setup Enable Bits Process Process/Macro NameType Description INIT_FORCED_MASK Internal Used to setup all of the bitsthat will be masked off from use in the randomizer Calculations.Requires INPUT_DATA_LENGTH, MASK_ON_CYCLE_REG, and MASK_OFF_CYCLE_REG befinalized. INIT_PROG_MASK Internal Used to calculate the impact of allbits in each Programmable mask register that is enabled. This must bedone any time a brought new equation is into the system. It should alsobe done on initialization, once all of the Selective Mask Registers havebeen initialized.Equation Mapper

The equation mapper takes the latest pattern in the input register, aspost operated on by the masking logic, and maps it through a giant XORgate logic tree to derive a corresponding randomizer value. On average,each randomizer output bit is made up of half the input data bits. Inthis case, each output is the XOR of 512 inputs. An XOR tree for 512inputs takes a total of (256+128+64+32+16+8+4+2+1=) 511 two input XORgates. Each mapping uses 16 bits, or a total of (16*511=) 8176 gates toproduce the randomizer output. When more and more equations are used,there is significant redundancy in the logic gates making up this XORtree.

The analysis shown in Tables AR and AS below breaks down the tree intolevels. The first level operates on groups of two inputs from the inputdata pattern. If these inputs are referred to as A and B, there is asingle XOR term possible (A XOR B), and there are two single terms thatflow through to the next level: A and B. At the second level of thetree, one can view the combinations of the groups (A,B) and (C,D). Thereare a total of six inputs for this block at the second level (A, B, AXOR B, C, D and C XOR D). When working with the tree, each of the inputsfrom the A,B group can be XOR'd with each of the inputs from the C,Dgroup. This results in a total of nine possible XOR terms at this level.The output terms from each higher level=(Output Terms from previouslevel ^^2+2*Output terms from previous level). The 2*Output terms fromprevious level accounts for the pass through values.

TABLE AR Size for 1024 Equations Number Max Max XOR XOR Maximum ofOutput Terms Per Gates/Level Inputs Output XOR Blocks Terms Block(*Number of per Terms from Terms for 1024 limited by Limited by Blocksfor Level Block each Block Per Block Inputs Equations Equations 1024Inputs) 1 2   3   1 512 3 1 512 2 4   15   9 256 15 9 2304 3 8  255  225128 255 225 28800 4 16 65535 65025 64 1024 1024 65536 5 32 4.29E9 4.29E932 1024 1024 32768 6 64 1.84E+19 1.84E+19 16 1024 1024 16384 7 1283.40E+38 3.40E+38 8 1024 1024 8192 8 256 1.16E+77 1.16E+77 4 1024 10244096 9 512 1.34E+154 1.34E+154 2 1024 1024 2048 10 1024 OverflowOverflow 1 1024 1024 1024 Total Number of XOR Gates in Tree per OutputBit 161,664 Total Number of XOR Gates for Entire Tree 2,586,624

TABLE AS Size for 128 Equations Number Max Max XOR XOR Maximum of OutputTerms Per Gates/Level Inputs Output XOR Blocks Terms Block (*Number ofper Terms from Terms for 1024 limited by Limited by Blocks for LevelBlock each Block Per Block Inputs Equations Equations 1024 Inputs) 1 2     3      1 512 3 1 512 2 4     15      9 256 15 9 2304 3 8     255    225 128 128 128 16384 4 16    65535    65025 64 128 128 8192 5 324294967295 4294836225 32 128 128 4096 6 64 1.84467E+19 1.84467E+19 16128 128 2048 7 128 3.40282E+38 3.40282E+38 8 128 128 1024 8 2561.15792E+77 1.15792E+77 4 128 128 512 9 512 1.3408E+154 1.3408E+154 2128 128 256 10 1024 Overflow Overflow 1 128 128 128 Total Number of XORGates in Tree per Output Bit 35,456 Total Number of XOR Gates for EntireTree 567,296Mapper Multiplexer

The mapper multiplexer circuitry must take equation mapper outputs andselect the appropriate randomizer bit pattern for the equation that isbeing used. The size of the mapper multiplexer is dependent upon thenumber of equations being used. The register sown in Table AT below isused to signify the mapping that is to be selected.

TABLE AT Internal Register to Select the equation Mapping Name SizeNotes EQUATION_MAP_SELECT 10 Bits This register is written by the systemto choose the equation mapping pattern to be used.

The mapper multiplexer size can be calculated using the formula that amultiplexer tree for 2^n bits contains 2^n−1 2:1 multiplexers. Table AUbelow shows the number of multiplexers that are needed as a function ofthe number of equations that are implemented.

TABLE AU Calculation of 2:1 Multiplexers needed as a function ofEquations Multiplexers per Total 2:1 Multiplexers Number of Equationsrandomizer Bit Required 128 127 2032 256 255 4080 512 511 8176 1024 102316368

The output of the equation multiplexer corresponds to the calculatedrandomizer value for the selected equation, and it is used to drive themapper storage control block.

TABLE AV Internal Signal name for the equation Multiplexer Output NameSize Notes CALC_RANDOMIZER_VALUE 16 Bits This output is the calculatedrandomizer value for the selected equation.Mapper Storage Control and Storage State Machine

The mapper storage control and storage state machine handles storing andretrieving randomizer values and associated table information. When newinputs are provided, the system must calculate and store randomizervalues for all equations of interest. When the system receives arandomizer value from the data framer, it must access these tables toidentify the proper input.

Primary Randomizer Output Vectors

The output of the primary randomizer is a 16-bit number that maps to aninput. For instance, if Input #5356 produces a value of 24593 in theprimary randomizer, then whenever the primary randomizer value of 24593is received, the system returns input #5356. Tables AW and AX below showhow inputs map when randomized by different equations (A, B, C, . . .n).

TABLE AW Primary randomizer mapping Table Primary Primary PrimaryPrimary randomizer randomizer randomizer randomizer Input # A Output BOutput C Output . . . “n” Output 1 1A 1B 1C 1n 2 2A 2B 2C 2n 3 3A 3B 3C3n 4 4A 4B 4C 4n 5 5A 5B 5C 5n 6 6A 6B 6C 6n 7 7A 7B 7C 7n . . . 10,00010000A 10000B 10000C 10000n

TABLE AX Primary randomizer Decoder Table Primary Primary Primaryrandomizer randomizer randomizer Output Vector A Map B Map . . . “n” Map   0 5356A x 4678n x x 8888n x x  589n x x 6688n    1  234A 3256B x3678A x x x x x x x x    2 x 7890B x x  576B x x x x x x x    3 9735A x2222n  121A x x 5678A x x x x x . . . 65,535 7764A  125B x x  987B x x xx x x x

In the above Table AX, there are six example locations with no inputsthat map into a specific state: A map 2, B map 0, B map 3, n map 1, nmap 2, and n map 65535. There are four example locations with one inputthat maps to a specific state: A map 0, A map 65535, B map 1, and n map3. There are three locations with two inputs that map to a specificstate: A map 1, B map 2, and B map 65535. There is one location wherethree inputs map into a specific state: A map 3. There is one locationwhere four inputs map into a specific state: n map 0.

The example in the above Table AX has a much higher rate of one, two,three, or four inputs being mapped into a specific state than would befound in an actual implementation. This has been done for illustrativepurposes only.

Primary Randomizer Table Entries

This discussion describes all of the entries in the primary randomizertable for the various possibilities of: no match, single match, pairmatch, triple match, quadruple match, overflow and masking (see TablesAY, AZ, and BA below).

TABLE AY primary randomizer Decoder Table Entry OFF- BIT BIT BIT BIT BITBIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT SET 15 14 13 12 11 10 9 8 76 5 4 3 2 1 0 0 STAT1 STAT0 Input Number 1 secondary randomizer ValueSTAT Bits

-   -   00 There is not a valid input that matches this value.    -   01 There is one valid match for this input, and it's secondary        Randomization pattern is contained in bits 0–13.    -   10 There are two valid matches for this input, and they are        stored in the Multiple Location found in bits 0–9.    -   11 There are three (or more) valid matches for this input, and        they are stored in the Multiple location found in bits 0–9.

TABLE AZ primary randomizer Decoder Table Entry for No Match BIT BIT BITBIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT OFFSET 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 0 0 0 XXX 1 XXX

TABLE BA primary randomizer Decoder Table Entry for Single Match BIT BITBIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT OFFSET 15 14 1312 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 Input Number 1 secondary randomizerNumber

The determination as to where to check the secondary randomizationpattern is left to a later time. This is due to the fact that the usercould chose to ignore the secondary randomization pattern. Of specialinterest is the case where a single match occurs that is a masking valueand not a final input value. This case is handled in theTriple/Overflow/Mask case, where there are sufficient bits to encode thesituation. In many ways, the MASK situation can be viewed as a multipleinput situation (see Table BB below).

TABLE BB Primary randomizer Decoder Table Entry for Pair Match BIT BITBIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT OFFSET 15 14 1312 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 XXX Multiple Match Table Entry 1 XXX

The Multiple Match Table Entry points to one of 1024 multiple matchtable entries (see Table BG below).

TABLE BC Primary randomizer Decoder Table Entry for Triple Match BIT BITBIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT OFFSET 15 14 1312 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 XXX Multiple Match Table Entry 1XXX

The Multiple Match Table Entry points to one of 1024 multiple matchtable entries (see Table BG below).

TABLE BD Primary randomizer Decoder Table Entry for quadruple Match BITBIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT OFFSET 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 1 XXX Multiple Match Table Entry1 XXX

The Multiple Match Table Entry points to one of 1024 multiple matchtable entries (see Table BG below).

TABLE BE Primary randomizer Decoder Table Entry for Overflows BIT BITBIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT OFFSET 15 14 1312 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 0 #Over Multiple Match Table Entry1 XXX

The multiple match table entry points into the multiple match table,with the exception that the table format changes so that only the inputnumbers are stored and not the secondary randomizer numbers. This allowsup to eight inputs to be stored. Because an overflow table entry evolvesfrom a quadruple table entry, one does not move the four inputs thatwere previously stored, but the new inputs overwrite the existingsecondary randomizer values in the structure.

The number of overflows(#Over) value specifies how many inputs arestored in what is normally the secondary randomizer section of themultiple match table entry structure. If there is a single overflow,this value is ‘01’. If there are two overflows this value is ‘10’, ifthere are three overflows this value is ‘11’, and if there are fouroverflows this value is ‘00’ (see Table BF below).

TABLE BF Primary randomizer Decoder Table Entry for Masking BIT BIT BITBIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT OFFSET 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 XXX Next Mask Step 1 secondaryrandomizer ValueMultiple Match Table

The custom ASIC uses a 1024 entry multiple match table (see Table BGbelow) to handle the cases where two, three, four, or the overflow caseof (5–8) input vectors map to the same primary randomizer output. Foreach possible pair, there are two possible inputs and associatedsecondary randomizer values that need to be stored. For each possibletriple, there are three possible inputs and associated secondaryrandomizer values that need to be stored. For each possible quadruple,there are four possible inputs and associated secondary randomizervalues that need to be stored. In cases of 5–8 inputs which aresignified as being overflow cases, the secondary randomizer values aredropped.

The primary randomizer table entry dictates the inputs and secondaryrandomizer values in the multiple match table entry that are valid.

TABLE BG Multiple Match Table Entry OFFSET B15 B14 B13 B12 B11 B10 B9 B8B7 B6 B5 B4 B3 B2 B1 B0 0 First Value secondary randomizer Output 1Second Value secondary randomizer Output 2 Third Value secondaryrandomizer Output 3 Fourth Value secondary randomizer Output 4 0 X FirstValue Input Pointer (Final Value) 1 XXX First Value Next Mask Step 5 0 XSecond Value Input Pointer (Final Value) 1 XXX Sec Value Next Mask Step6 0 X Third Value Input Pointer (Final Value) 1 XXX Th Value Next MaskStep 7 0 X Fourth Value Input Pointer (Final Value) 1 XXX Fth Value NextMask StepMultiple Match Table Valid Entries

The VALID_MULT_ARRAY (see Table BH below)stores information as to whichmultiple match table entries have been used by a particular mapping.There are 1024 multiple match table entries associated with eachmapping, and the VALID_MULT_ARRAY is therefore 1024/16=64 values long toidentify where there are open multiple entries. In addition, a secondstep of having four 16-bit values to signify where there are availableentries that are used. One could conceivably use a pointer or pair ofpointers in the ASIC to keep track of the next available inputs.

TABLE BH Valid Multiple Match Entry Array Table Offset 16 Bit ValueDescription Comments 0 First Block of Valid 0=Unused Table EntryMultiple Entry Tags Bit 0=Multiple Entry 0 (0–15) 1 Second Block of0=Unused Table Entry Valid Multiple Entry Bit 0=Multiple Entry 0 Tags(16–31) 63 Sixty Fourth Block of Valid 0=Unused Table Entry MultipleEntry Tags) Bit 0=Multiple Entry 0 (1007–1023 64 Super Block Descriptorfor 0=Unused Table Entry in Block Blocks (0–15) 65 Super BlockDescriptor for ″ Blocks (16–31) 66 Super Block Descriptor for ″ Blocks(32–47) 67 Super Block Descriptor for ″ Blocks (48–63)Storage Required for Each Equation

Table BI below shows the memory storage required for each mapping thatis stored.

TABLE BI Storage Associated with Each primary Mapping Offset BlockLength Comments 0 primary randomizer 131072 Two 16 Bit words per DecoderTable primary randomizer State. 131072 Multiple Match Table 8192 Eight16 Bit words per Multiple Match Table Entry 139264 Valid Pair ArrayTable 68 Identifies entries in the Multiple Match Table that are used.139332 mapping EndRegisters Used in Storing and Reading a New Randomizer Entry

Table BJ below lists the registers used to access and modify therandomizer table. The output of the mapper is the CALC_RANDOMIZER_VALUE.The selection of the equation mapper uses the EQUATION_MAP_SELECTregister. The storage value is EQUATION_STORE_ENTRY which dictates wherethe value is stored in the primary randomizer table. In the case ofstoring a new value into the randomizer table, the INPUT_DATA_NUMBER isthe output of a multiplexer that selects between theUSER_INPUT_DATA_NUMBER and the SYS_INPUT_DATA_NUMBER and it contains theinput number for the value while the PRESENT_MASK_STEP andNEXT_MASK_STEP store the necessary masking information.

When interpreting a randomizer value from the data framer, theRANDOMIZER_SELECT value is used to determine whether to analyze theprimary or secondary randomizer values. The PRIM_RANDOMIZER_RX registercontains the primary randomizer value, and the SEC_RANDOMIZER_RXregister contains the secondary randomizer value. The PROG_MASK_RXsignal is the masked value of the received primary or secondaryrandomizer signal (see Table BJ below).

TABLE BJ Randomizer Control Registers NAME SIZE COMMENTSPRIM_RAND_TABLE_BASE 32 Bits Located on Fire-Hose 10K ASIC. UserRead/Writeable This is the base address in SRAM of the primaryrandomizer Table. It is variable to permit the user the set it up at anylocation in memory. PRIM_RAND_LENGTH 32 Bits Located on Fire-Hose 10KASIC. User Readable This is the length in bytes of a primary randomizerTable for a single equation PRIM_RAND_LOCATION 32 Bits Located onFire-Hose 10K ASIC. This register stores the location in the primaryrandomizer table that is being addressed by the primary randomizer ValuePRIM_RAND_ENTRY 16 Bits The value that is stored in a primary randomizerLocation. MULT_TABLE_OFFSET 32 Bits The Offset from the base primaryrandomizer Table Entry for the Multiple Entry Table. This is a fixedconstant. MULT_VALID_OFFSET 32 Bits The Offset from the base primaryrandomizer Table Entry for the Multiple Entry Valid Table. This is afixed constant. TEMP_POINTER0 32 Bits This pointer is used as a secondpointer for creating new inputs in the primary Randomization Table.TEMP_POINTER1 32 Bits This pointer is used as a third pointer forcreating new inputs in the primary Randomization Table TEMP_VALUE0 16Bits This register is used as a temporary 16 bit storage for SRAM reads.TEMP_VALUE1 16 Bits This register is used as a temporary 16 bit storagefor SRAM reads. TEMP_ENCODE0  5 Bits This is an encoded value showingthe lowest unused position in a 16 bit word. The 5^(th) bit is used tosignify that there are none available. TEMP_ENCODE1  5 Bits This is anencoded value showing the lowest unused position in a 16 bit word. The5^(th) bit is used to signify that there are none available. TEMP_COUNT16 Bits This is a temporary counter used to help walk through theMultiple Tables.Registers Associated with Initializing all Randomizer Mappings

The following registers are associated with clearing out a randomizertable and with clearing out the multiple table entries for any equation.Due to the fact that the system may be dynamically clearing out anequation entry in the middle of updating new equations, it is importantthat there be independent registers to point into the SRAM for theinitialization process (see Table BK below).

TABLE BK Randomizer Initialization Registers NAME SIZE COMMENTSRAND_INIT_VALUE 16 Bits This is the value that will be stored intomemory for the randomizer table during initialization. RAND_INIT_ADDRESS32 Bits This is the present address in the randomizer table thatinitialization values are being stored into. RAND_INIT_COUNT 16 BitsThis is a counter variable used in clearing out a randomizer TableValue. RAND_INIT_EQ  8 Bits This is used to maintain the equation numberof a randomizer Table that is being cleared.Processes for Randomizer Table Manipulations

There are a number of independent operations to manipulate the primaryrandomizer tables. These involve initialization, storage and retrievalof data (see Table BK below).

TABLE BK Processes for randomizer Table Manipulations Process Name TypeDescription RAND_INIT Internal Used to Initialize and clear out arandomizer Table for one specific equation. PRAND_ADD_ENTRY InternalAdds a randomizer Table Entry for a single equation and mapping.GET_NEW_MULT_ENTRY Internal Used to find and tag the next availableMultiple Table Entry for the specific equation that is being operatedon. PRAND_SUB_ENTRY Internal Subtracts an input value from the primaryrandomizer Table for a single equation and mapping. CLEAR_MULT_ENTRYInternal Used to free up a Multiple Table Entry location.IDENTIFY_MULT_INPUT Internal Used to identify the position in a MultipleTable Entry where the specific input or mask step is located.Mapper Engine, Statistics and Equation State Machine

The purpose of the mapper engine, statistics, and equation state machineis to cycle through the various equation mappings for new inputs,maintain statistics for each equation mapping, select the appropriateequations to use, and initiate swapping out equations that do notproduce appropriate mappings. This block has a state machine thatoperates on inputs across all equations. It implements counters inhardware to maintain statistics for each equation.

Primary Randomizer Equation Analysis

The system maintains data for a total window of eight primary randomizerequations on-chip. The system selects between these eight mappings topick the best one using a variety of characteristics. Each of theseequations have counters associated with the number of triples,quadruples, or overflow values that they contain. Based uponprogrammable criteria (values written into registers), the user candecide how often an equation is deemed to be non-usable and a search isinitiated for a replacement. This directly affects power consumptionbecause any time a search for a better equation is done, there are alarge number of accesses to DRAM. On the flip side of the equation, whenthe equation set is static, there is extremely low power consumptionfrom the custom ASIC.

Equation Status Counters

The following set of counters (Table BL below) is maintained for eachequation on the custom ASIC. The output of these registers is used todetermine the best equation for use, and whether certain equations needto be switched out.

TABLE BL Equation Status Counters/Registers Register Name BitsDescription EQ0_TRIPS 8 Counts the number of triples for equation 0 Avalue of 255 disables the equation from use. EQ0_QUADS 6 Counts thenumber of quadruples for equation 0 A value of 63 disables the equationfrom use. EQ0_MULTS 10 Counts the number of Multiple Entries forequation 0 A value of 1023 disables the equation from use. EQ0_(—) 2Counts the number of Overflow Entries for OVERFLOW equation 0. A valueof 3 disables the equation from use. EQ0_(—) 1 Register bit to indicatewhether the equation is COMPLETE complete in terms of implementing allinputs. . . . . . . . . . EQ7_TRIPS 8 Counts the number of triples forequation 7 EQ7_QUADS 5 Counts the number of quadruples for equation 7 Avalue of 32 disables the equation from use. EQ7_MULTS 10 Counts thenumber of Multiple Entries for equation 7 A value of 1023 disables theequation from use. EQ7_(—) 2 Counts the number of Overflow Entries forOVERFLOW equation 7. A value of 3 disables the equation from use.EQ7_(—) 1 Register bit to indicate whether the equation is COMPLETEcomplete in terms of implementing all inputs.

The following error conditions are serious for a specific equation, andmust be handled quickly by the custom ASIC:

-   -   The number of Overflow Entries (EQn_OVERFLOW) exceeds 0    -   The number of Multiple Entries (EQn_MULTS) exceeds 1024

In the worst case, a serious error results in an incoming packet notbeing identified by the custom ASIC. Any of the errors listed abovewould result in a vector not being found in the primary mapping table. Alarge majority of packets, i.e. 9999/10000, would still continue to bereceived as expected, and quickly, the chip would change the primarymapping equation to handle the serious fault.

Optimal Primary Equation Selection

The issues associated with picking the optimal primary equation arenumerous. The greater the number of multiple entries, the longer theaverage lookup time is for the equation and the greater the probabilitythat the multiple table entries is exceeded. The number of quadruples isan early indicator of possible problems because a quadruple is a singlenew input vector away from creating a serious error condition. Anyequation that has reached an overflow condition for must be eliminatedout of hand if possible. If no equation meets these criteria, then it iscritical that the least offensive of the remaining equations be used. Itis also critical that only equation mappings that contain all inputs beconsidered in this evaluation. This is necessary because there are timeswhen equations are swapped out, and new ones are evaluated.

The following equation shows how the EQm_DISABLE bit is calculated. Thisbit is necessary to be able to shut down the use of equations that areinappropriate. The thresholds for quadruples and triples have been setto very high levels that have an extremely low probability of occurrencein real life, and that pose a added burden to the receiver should theybe used.EQm_DISABLE=(EQm_OVERFLOW==3)∥(EQm_MULTS==1023)∥(EQm_QUADS==63)∥(EQm_TRIPS==255))

The equation optimization comparator input word for each of the eightpossible equations has been designed so that the best equation is theone with the lowest word. This way, the eight equation optimizationcomparator input words can be sent through a 4->2->1 tree of 2:1comparators to determine the optimal equation. In looking at the word,the highest priority for disqualification occurs when the equation tableis incomplete. The second highest priority is that the equation has beendisabled due to either overflow conditions or an excessive number ofquadruple or triple matches. Next, the number of overflow conditions isused, which it is hoped is zero. The number of multiple inputs comesnext in the priority structure, followed by the number of quadruples andtriples in that order.

The equation optimization comparator produces the OPTIMAL_EQUATIONoutput that signifies the best equation mapping at the present time (seeTable BM).

TABLE BM Equation Optimization Comparator Inputs (equation 0 Example)Word Section MSB LSB EQm_INPUT EQm_(—) EQm_(—) EQm_(—) EQm_(—) EQm_(—)EQm_TRIPS INCOMPLETE DISABLE OVERFLOW MULTS QUADS

The system identifies equations that are not usable, i.e.EQm_DISABLE==1, and determines when they reach a threshold programmed bythe user (EQ_UPDATE_THRESH). When this threshold is reached, the systemsets the EQm_INCOMPLETE bit for each disabled equation, clears out thedisabled equations, and then updates the disabled equation (see Table BNbelow). This decision process also relies on equation aging which isdescribed below.

TABLE BN Registers associated with Updating Equations Address RegisterName Bits Notes 0xA0 EQ_UPDATE_THRESH 3 When this threshold is reached,the system will update all equations that have been disabledOPTIMAL_EQUATION 3 This is the output of the equation OptimizationComparator, and tells which of the equations is the best.SECOND_BEST_EQUATION 3 This is an output of the equation OptimizationComparator, and tells which of the equations is the second best.EQ_INPUT_COUNT 16 Used to count through the inputs when updating a setof equations EQ_POINTER 3 Points to the equation being operated onpresently. PRIM_RAND_VALUE 16 primary randomizer value that is a latchedvalue of the CALC_RANDOMIZER_VALUE SEC_RAND_VALUE 16 secondaryrandomizer value that is a latched value of the CALC_RANDOMIZER_VALUEMethod to Track Mappings to Equation Values

There are eight different primary equation mappings that are used at anytime by the custom ASIC. These equations map to one of 128 equationsthat are implemented in the mapper, which in turn map to one of the32768 possible feedback paths for the randomizers. Actually, theimportant thing is that one stores a secondary mapping with each tablefor reference, and a way to determine whether there are duplicates.Storing whether a secondary mapping produced a duplicate would require anew bit. Primary and secondary randomizer values must be stored in theequation map for use because it is necessary to have their mask impactbits available on custom ASIC. Therefore, one needs to make sure thatrecently used primary and secondary randomizer equations are available.

Table BO below lists the registers associated with storing the mappinginformation. These values can be directly applied to the mappermultiplexer to determine the value. The system has 128 possiblemappings, and uses a total of eight equations that each correspond toone of the mappings. Any time that an equation is found to be bad, avalue of eight is added to the equation number. This guarantees that onewill never have two equations that map to the same value. At any giventime, one should use the best available mapping as the secondaryrandomizer equation value for new equations. The odds of this equationgoing bad is significantly less than other equations in the table, andthe problem of being forced to keep it around has similarly less impact.

TABLE BO Registers that Store the Relation between mapper values andEquations Register Name Bits Notes EQ0_PRIM_MAP 8 Value of 0–127corresponding to the primary randomizer mapping used for equation 0.EQ0_SEC_EQ_NUM 4 Identifies which of the 8primary map Equations is beingused as the secondary randomizer equation for equation 0. The MSBsignifies that the equation is no longer valid when it is set to a 1.EQ1_PRIM_MAP 8 Value of 0–127 corresponding to the primary randomizermapping used for equation 0. EQ1_SEC_EQ_NUM 4 Identifies which of the8primary map Equations is being used as the secondary randomizerequation for equation 1. The MSB signifies that the equation is nolonger valid when it is set to a 1. . . . . . . . . . EQ7_PRIM_MAP 8Value of 0–127 corresponding to the primary randomizer mapping used forequation 7. EQ7_SEC_EQ_NUM 4 Identifies which of the 8primary mapEquations is being used as the secondary randomizer equation forequation 7. The MSB signifies that the equation is no longer valid whenit is set to a 1.Maintenance of Equation Mappings

It is critical to maintain primary randomizer equation mappings thathave been sent to the data framer for a reasonable time period. This isnecessary to avoid a problem where an equation is swapped out and avalue is read from the data framer that has no corresponding table forevaluation. In the case of parallel modes of operation, it is possibleto use any of the equations and this is not a problem.

When a user is using the data framer, it is presumed that there is atime critical nature to the analysis of data packets. For this reason,it is possible to use a set of timers for each equation to indicate howlong ago the equation was used in a data framer. These timers are amaximum of one second in length, and once one second has expired, theequation is considered as having been aged out. In the future, it may bevaluable to permit a programmably variable shorter time to indicate thatan equation has been aged out.

The equation aging registers are clocked at a 4 msec rate. When newprimary and new secondary randomizer equations are written into the dataframer, their equation aging registers are set to 0. The primary andsecondary randomizer equations that are used for the data framer are bethe ones used for parallel classification. All other equation agingregisters are permitted to count upward. When an equation aging registercounts up to a value of 255, it stops to signify that the counter hasaged out (see Table BP below).

TABLE BP Registers Associated with equation Aging Register Name BitsNotes EQ0_AGING 8 8 bits of counter, and the MSB bit shows that theequation has aged out. EQ1_AGING 8 8 bits of counter, and the MSB bitshows that the equation has aged out. . . . . . . . . . EQ7_AGING 8 8bits of counter, and the MSB bit shows that the equation has aged out.Processes Used for Mapping Analysis

There are a number of processes associated with initializing andmaintaining information regarding the equations used by the system (seeTable BQ below).

TABLE BQ Processes used for mapping Analysis Process/Macro Name TypeDescription INITIALIZE_ONE_EQ Internal Initializes the mapping andStatistics registers used for a single equation INITIALIZE_ALL_EQInternal Initializes all of the equations being used in the system.ADD_INPUT_ALL_EQ Internal Handles mapping and storing an input for allsets of equations. SUB_INPUT_ALL_EQ Internal Handles mapping andremoving an input for all sets of equations. UPDATE_DISABLED_EQSInternal This process is used to update equations that are no longervalid. It is not called until a certain programmable threshold ofequations are disabled.Time Accelerator Block

The purpose of the time accelerator block is to advance a receivedrandomizer value through “n” cycles of time in a single hardware cycleon the custom ASIC. The custom ASIC is running at extremely high speeds,and it is desirable to shut down the randomizers whenever possible toavoid power consumption. The calculated randomizer values in the customASIC are based upon a 1024-bit input word being used for thecalculations, with all 1024 input bits being shifted into therandomizer. The custom ASIC has been structured such that bits occurringafter the user selected data length are set to zero in the calculation(see FIG. 16). Therefore, to produce an equivalent result the dataframer would be required to clock in the equivalent number of trailingzeros to it's randomizer. This clocking of trailing zeros could resultin significant power consumption, and would result in additional latencybetween the reception of the packet header and identification of thematching input.

To solve this problem, the time accelerator block has been added to thecustom ASIC. This block is able to take a randomizer value and shift itforward by the equivalent of “n” cycles of zero clocked input data allwithin a single cycle. The theory behind this time acceleration revolvesaround the fact that any shift of “n” cycles can be viewed as aremapping of the initial state of the randomizer stage values (qinit0,qinit1, . . . qinit15). To shift forward by a specific time of “n”cycles requires a specific remapping of the initial values to the finalvalues. To accomplish a variable shift of any chosen value of “n”cycles, the novel custom ASIC implements a binary weighted programmableshifter. To accomplish a variable shift of from 1 to 1024 bits inlength, the system implements a 512-bit shifter, a 256-bit shifter, a128-bit shifter, a 64-bit shifter, a 32-bit shifter, a 16 bit -shifter,an 8-bit shifter, a 4-bit shifter, a 2-bit shifter, and a 1-bit shifter.Based on the selected shift value “n”, each of these fixed shifterstages is either switched into the data path or bypassed. Each shifterstage relies entirely on its own inputs to produce a direct mapping toits own outputs. There is no interaction between groups of stages otherthan the fact that the individual stages are producing a one-to-onemapping of inputs to outputs. To simplify this block, and the timeassociated with making calculations, the time accelerator may bemodified to advance in 32-bit increments only. This would permit 512-bitshifts, 256-bit shifts, 128-bit shifts, 64-bit shifts, and 32-bit shiftsonly, but does nothing to affect the theory of operation for this block.

Time Accelerator Register

The TIME_ACC_CYCLE is used to setup the number of cycles of accelerationto be applied to a received randomizer value. The source of the timeaccelerator block is chosen by the RANDOMIZER_SELECT value that choosesbetween the primary and secondary randomizer values that have beenreceived. The equation that is being used in the analysis of therandomizer is critical for determining the mapping, and it is stored inthe EQUATION_STORE_ENTRY register (see Table BR below).

TABLE BR Registers associated with Time Acceleration Register Name BitsNotes TIME_ACC_(—) 10 Value of 0 to 1023 that contains the number ofCYCLE cycles that the primary and secondary randomizers need to beadvanced through under the condition of having a zero input.Time Accelerator Logic Stage

The preferred implementation of one of the time accelerator stages usinga large number of XOR gates and a smaller number of multiplexers (seeFIG. 14). The input to the stage is qstagein[15:0] which can be eitherthe output of a previous stage, or an actual randomizer value. The stageconsists of 128 mappings of qstagein[15:0] to qstageout[15:0] to handleeach of the possible equation mappings. Each of the bits inqstageout[15:0] is a function of qstagein[15:0], and can be implementedwith an XOR tree of all of the applicable bits. For instance,qstageout[0] may be qstagein[0]+qstagein[3]+qstagein[7]+qstagein[1]which can be implemented with XOR gates. Each of the possible outputs isa function of qstagein[n], and uses half of the inputs on average. Oncethe outputs for all 128 equations have been calculated, a 128:1multiplexer chooses the correct output for the equation beingconsidered.

The example above shows how an individual bit in the output iscalculated. This is multiplied by sixteen to handle each output bit inthe remapping situation. The benefit of this approach is that the XORtrees for all of the equations, and for all of the output bits areshared. There is a limit to how many XOR gates can be used when thereare a total of only sixteen inputs.

TABLE BS Size for 16 Bits Max Max XOR XOR Output Terms Per Gates/LevelInputs Output Maximum Number of Terms Block (*Number of per Terms fromXOR Terms Blocks for limited by Limited by Blocks for Level Block eachBlock Per Block 16 Inputs Equations Equations 16 Inputs) 1 2 3 1 8 3 1 82 4 15 9 4 15 9 36 3 8 255 225 2 128 128 256 4 16 65535 65025 1 128 128128 Maximum Total XOR Gates Per Stage 428

This approach uses a maximum of 428 XOR gates in it's implementation forthe entire stage, and it uses only 16×128:1 multiplexers which eachcontain 127 2:1 multiplexers. This is a total of 2,460 gates per timingaccelerator stage.

Overall Timing Accelerator Architecture

The timing accelerator (See FIG. 15) uses a total of ten programmableshifter stages to calculate it's output. Each of these stages must beeither passed through or bypassed to achieve the desired result.

Interface

The interface provides the functions of configuring the data framer andreading and interpreting data when a packet is received.

In configuring the data framer, the data length must be provided. TheINPUT_DATA_LENGTH register described herein must be transferred to thedata framer upon initialization

In configuring the data framer, a set of masking registers need to beinitialized. The MASK_OFF_CYCLE_REG and MASK_ON_CYCLE_REG registers aredescribed herein. In addition, MASK_REGISTER_0, MASK_REGISTER_1,MASK_REGISTER_2 and MASK_REGISTER_3 are described in the context oftheir start values. These six masking registers have associated enablebits to determine whether or not they must be loaded into the dataframer. All masking registers are expected to be loaded into the dataframer upon initialization or reset, but are not expected to be changedduring operation.

In addition to the MASK and length registers, the data framer randomizerfeedback registers must be configured. These are described in Table BTbelow, and their calculation is described later in this discussion.

TABLE BT Additional Registers to be written into the data framer forConfiguration Address Register Name Bits Notes 0x00 PRIME_RAND_(—) 16Value to be latched into the FEEDBACK data framer ASIC for the primaryrandomizer Feedback. 0x01 SEC_RAND_(—) 16 Value to be latched into theFEEDBACK data framer ASIC for the secondary randomizer Feedback.

In receive mode, the custom ASIC latches data from the data framer sothat it can be analyzed. A FIFO structure may be necessary to permitpackets to back up if necessary. With the new parallel mode ofoperation, it becomes more likely that an operation may precludeimmediate access to the randomizer state machines because many channelscould be using the same custom ASIC. Ideally, the interface always hasthe highest priority because it is the high performance interface. Theimplementation that is listed below supports storing a single registersnapshot, but it could be easily increased to being a set of FIFOs.

In receive mode, the received randomizer values must be read from thedata framer. The discussion herein describes the PRIM_RANDOMIZER_RX andthe SEC_RANDOMIZER_RX registers that contain these two values. Inaddition, mask capture data must be received from the data framer, andthis is stored in the MASK_CAPTURE_DATA_0, MASK_CAPTURE_DATA_1,MASK_CAPTURE_DATA_2 and MASK_CAPTURE_DATA_3 registers that are describedherein.

Finally, the custom ASIC must know the randomizer feedback values thatwere used in calculating the primary and secondary randomizer values. Ifthe feedback values have changed because the last packet, then a flag isset in the interface to show that these should be read. Otherwise, thecustom ASIC can chose not to read these values. The description of theseregisters is found in Table BU below.

TABLE BU Additional Registers to be read from the data framer AddressRegister Name Bits Notes 0x02 FLAME_PRIM_FB 16 randomizer feedback fromthe data framer ASIC that was used to calculate the primary randomizervalue. 0x03 FLAME_SEC_FB 16 randomizer feedback from the data framerASIC that was used to calculate the secondary randomizer value.Equation Recovery Section

The feedback value that is returned from the data framer must beconverted into a relative equation number from 0 to 7 that points to aprimary randomizer table. To execute this feature, eight feedbackregister values must be stored along with their equation mapping (seeTable BV below and FIG. 16).

TABLE BV Registers associated with equation Recovery Register Name BitsNotes EQ0_FEEDBACK 16 EQ0 primary randomizer Feedback EQ1_FEEDBACK 16EQ1 primary randomizer Feedback . . . EQ7_FEEDBACK 16 EQ7 primaryrandomizer Feedback EQ_REC_SEL 1 Selects the randomizer feedback sourceto be used to determine the original equation. PRIM_RAND_(—) 4 Theequation Number for the primary EQ_NUM randomizer in the data framerASIC. MSB indicates validity. SEC_RAND_EQ_(—) 4 The for the secondaryrandomizer in the data NUM framer ASIC. MSB indicates validity.Randomizer Setup Section

Given the equation number, the proper EQn_FEEDBACK register can beselected to drive the data framer. This section shares the equationfeedback registers with the equation recovery section. TheOPTIMAL_EQUATION is driven in logic, and it is used to select thePRIM_RAND_FEEDBACK (see FIG. 17). At the time that the primaryrandomizer table is stored for the OPTIMAL_EQUATION, a specificsecondary randomizer is used, and this is stored in theEQ[OPTIMAL_EQUATION]_SEC_EQ_NUM register. The frequency that thePRIM_RAND_FEEDBACK and SEC_RAND_FEEDBACK is updated with theUPDATE_FEEDBACK signal is no faster than the time required to load,calculate, and store or remove an input value. The feedback values onlyneed to be updated when a change is made to the randomizer tables.

Processes Associated with the Interface

The updating of the interface registers should be done as infrequentlyas possible to avoid churning. When a new equation is desired, newfeedback registers must be latched into the data framer. Oninitialization, it is also necessary to load masking registers into thedata framer.

Detailed State Diagrams

In all cases below, the process implementation tables are organized inthe form: State name—activity—next state, whether or not statusindicated in a Table heading.

State Machines for the “Input Manager Control and State Machines” Block

The following state machines are used to manage the user inputs in thesystem (see Tables BW-CN below).

TABLE BW INPUT_VALID_INIT - Process Description Process NameINPUT_VALID_INIT Process Function This Process is called to initializethe Input Valid Table so that all entries are 0. This reflects the factthat at power up, there are no input values stored in the system. ReturnValue(s) none Required Inputs none Modified INPUT_STRUCT_PTR RegistersINPUT_VALID array INPUT_CONTROL_REG Error Conditions None

TABLE BX INPUT_VALID_INIT - Process Implementation STATE NAME ACTIVITYNEXT STATE IDLE If the Input Control Register Command START field is setto “Initialize Input Valid PROCESS Array”. Set the “Command Complete”bit to a 0 to signify that the system is Initializing. Else IDLESTART_PROCESS Load the INPUT_VALID_BASE into CLEAR_ARRAYINPUT_STRUCT_PTR. The INPUT_STRUCT_PTR now points to the first locationin the INPUT_VALID array. CLEAR_ARRAY Write a 0 into the 32 bit locationINCREMENT_SEARCH addressed by the INPUT_STRUCT_PTR. INCREMENT_SEARCH Adda value of 4 to the CONDITION_PTR INPUT_STRUCT_PTR. CONDITION_PTR Checkthe value that is stored in the INPUT_STRUCT_PTR location. IfINPUT_STRUCT_PTR>= IDLE {INPUT_VALID_BASE+313} Set the “CommandComplete” bit in the INPUT_CONTROL_REG to a 1 to show that theinitialization is completed. Else CLEAR_ARRAY This is a valid value, andthe system will continue initializing

TABLE BY USER_CHECK_VALID - Process Description Process NameUSER_CHECK_VALID Process Function This Process is called by the user todetermine whether an input location contains a valid input. ReturnValue(s) INPUT_CONTROL_REG, “Input Valid” bit Required InputsUSER_INPUT_DATA_NUMBER Modified Registers INPUT_STRUCT_PTRINPUT_STRUCT_VALUE INPUT_CONTROL_REG, “Input Valid” bit Error ConditionsInvalid Input.

TABLE BZ USER_CHECK_VALID - Process Implementation STATE NAME ACTIVITYNEXT STATE IDLE If the INPUT_CONTROL_REG CHECK_INPUT_VALUE “Command”field is set to “Check Input Valid”, set the “Command Complete” bit to0. Set INPUT_NUM_SOURCE_SEL=0 {Selects user Input} Else IDLECHECK_INPUT_VALUE If (INPUT_DATA_NUMBER>10,000) INVALID_INPUT ElseCALC_POINTER CALC_POINTER Load INPUT_VALID_BASE+ GET_VALID_ENTRYINPUT_DATA_NUMBER >>5 into the INPUT_STRUCT_PTR. This will contain theaddress of the appropriate Valid word. GET_VALID_ENTRY Read the value inDRAM that is addressed CALC_VALID_MASK by INPUT_STRUCT_PTR and store itin INPUT_STRUCT_VALUE. CALC_VALID_MASK The INPUT_STRUCT_VALUE now IDLEcontains information on 32 different inputs. INPUT_DATA_NUMBER[4:0]distinguishes which of these inputs is being addressed. ApplyINPUT_DATA_NUMBER[4:0] to the 32 bit decoder. AND INPUT_STRUCT_VALUEwith the 32 bit decoder output, and make a decision based upon theoutput. If Result=1, then there is a “1” stored in the location and theinput is valid. If Result=0, then there is a “0” stored in the locationand the input is not valid. Store the result in the INPUT_CONTROL_REG“Input Valid” bit. INVALID_INPUT Set an interrupt to tell the user thatthe IDLE input was not valid. Write a “0” to the INPUT_CONTROL_REG“Input Valid” bit because this is not a valid input.

TABLE CA SYS_CHECK_VALID - Process Description Process NameSYS_CHECK_VALID Process Function This Process is called by the system todetermine whether an input location contains a valid input. ReturnValue(s) INPUT_STRUCT_VALUE - 1=Valid Input, 0=Unused Input RequiredInputs SYS_INPUT_DATA_NUMBER {contains the input to be checked} ModifiedRegisters INPUT_STRUCT_PTR INPUT_STRUCT_VALUE Error Conditions None{System is assumed to generate a valid input}

TABLE CB SYS_CHECK_VALID - Process Implementation STATE NAME ACTIVITYNEXT STATE BEGIN INPUT_NUM_SOURCE_SEL=1 {Selects the START_PROCESSSYS_INPUT_DATA_NUMBER} START_PROCESS Load INPUT_VALID_BASE+GET_VALID_ENTRY INPUT_DATA_NUMBER >>5 into the INPUT_STRUCT_PTR. Thiswill contain the address of the appropriate Valid word. GET_VALID_ENTRYRead the value in DRAM that is addressed by CALC_VALID_(—)INPUT_STRUCT_PTR and store it in MASK INPUT_STRUCT_VALUE.CALC_VALID_MASK The INPUT_STRUCT_VALUE now contains END information on32 different inputs. INPUT_DATA_NUMBER[4:0] distinguishes which of theseinputs is being addressed. Apply INPUT_DATA_NUMBER[4:0] to the 32 bitdecoder. AND INPUT_STRUCT_VALUE with the 32 bit decoder output, and makea decision based upon the output. If Result=1, then there is a “1”stored in the location and the input is valid. If Result=0, then thereis a “0” stored in the location and the input is not valid. Write Resultinto INPUT_STRUCT_VALUE as a return value.

TABLE CC SYS_GET_AVAIL_INPUT - Process Description Process NameSYS_GET_AVAIL_INPUT Process Function This Process is called by thesystem to determine the next open input location within the inputstructure. Return Value(s) INPUT_AUTO_LOCATION - Next available input.INPUT_CONTROL_REG - “Unused Input” bit. Required Inputs none ModifiedRegisters INPUT_STRUCT_PTR INPUT_STRUCT_VALUE INPUT_VALID_ENCODEINPUT_AUTO_LOCATION INPUT_CONTROL_REG - “Unused Input”, “Inputs Full”and “Wrap” bits. Error Conditions “Inputs Full” - There are no availableinputs. Pointer conditioning for overflow and underflow.

TABLE CD SYS_GET_AVAIL_INPUT - Process Implementation STATE NAMEACTIVITY NEXT STATE IDLE If the “Unused Input” bit in the START_PROCESSINPUT_CONTROL_REG is a 0 which shows that there is not an availableinput. Set the Wrap bit in the Input Control Register to 0 to signifythat the system has not wrapped around in it’s search. Else IDLESTART_PROCESS Load INPUT_VALID_BASE into the GET_VALID_ENTRYINPUT_STRUCT_PTR The INPUT_STRUCT_PTR now points to the first locationin the INPUT_VALID array. GET_VALID_ENTRY Read the value in DRAM that isaddressed CHECK VALID_ENTRY by INPUT_STRUCT_PTR and store it inINPUT_STRUCT_VALUE CHECK_VALID_ENTRY The INPUT_STRUCT_VALUE is appliedto a Priority Encoder which will determine the lowest entry in the wordthat is non- one (available) if such a value exists. If No Valid Entriesin this word INCREMENT_SEARCH If Valid Entry, then store the prioritizedCALC_OPEN_LOCATION value in INPUT_VALID_ENCODE. CALC_OPEN_LOCATIONINPUT_AUTO_LOCATION=(INPUT_STRUCT_(—) IDLE PTR-INPUT_VALID_BASE)*32+INPUT_VALID_(—) ENCODE Set the “Unused Input” bitto a 1 in the Input Control Register to signify that theINPUT_AUTO_LOCATION register has the next available input.INCREMENT_SEARCH Add a 1 to the INPUT_STRUCT_PTR to CONDITION_PTRprepare to search the next entry. CONDITION_PTR Check the value that isstored in the INPUT_STRUCT_PTR location to make sure that it is a validpointer for the Input Valid array. If INPUT_STRUCT_PTR< UNDERFLOW_ERRORINPUT_VALID_BASE INPUT_STRUCT_PTR=INPUT_VALID_BASE This is an underflowerror condition. That should never happen and indicates something isseriously wrong. If GET_VALID_ENTRY INPUT_STRUCT_PTR>=(INPUT_VALID_(—)BASE+313) and the Wrap bit in the Input Control Register=0. SetINPUT_STRUCT_PTR=INPUT_VALID_BASE (The system has overflowed the arraypointer and it has not wrapped around, so the array pointer will be setback to the beginning of the array and start searching again) IfFULL_ARRAY INPUT_STRUCT_PTR>=(INPUT_VALID_(—) BASE+313) and the Wrap bitin the Input Control Register==1 (The system has overflowed the arraypointer and it has wrapped around, so the system will stop searchingbecause there are no available openings.) If GET_VALID_ENTRY(INPUT_STRUCT_PTR>=INPUT_VALID_(—) BASE) &&(INPUT_STRUCT_PTR<(INPUT_VALID_(—) BASE+313*4)) (This is a valid value,and processing will continue) UNDERFLOW_ERROR This is a critical problembecause a IDLE counter has clearly been corrupted. One possibility isthat the INPUT_STRUCT_PTR has been changed in the middle of operation.If this is the case, the routine will generate an error interrupt andstop processing. Interrupt the host to signify that an error hasoccurred. FULL_ARRAY Set the “Inputs Full” bit in the Input Control IDLERegister to “1”. Interrupt the host to signify that an error hasoccurred.

TABLE CE USER_INPUT_WR_LOAD - Process Description Process NameUSER_INPUT_WR_LOAD Process Function This Process is called by the userto write a new input into the system and to have the input be loadedinto the Input Register. Return Value(s) Required InputsUSER_INPUT_DATA_NUMBER INPUT_STRUCT_VALUE PRESENT_MASK_STEPNEXT_MASK_STEP Modified Registers INPUT_STRUCT_PTR (This Process)INPUT_DATA_WORD_COUNT INPUT_CONTROL_REG —“Command”, “Buffer Full”,“Unused Input” and “I/O Ready” bits. INPUT_VALID_ENCODE ModifiedRegisters From ADD_INPUT_ALL_EQ Process (Sub-Processes) Error conditionsInvalid INPUT_DATA_NUMBER

TABLE CF USER_INPUT_WR_LOAD - Process Implementation STATE NAME ACTIVITYNEXT STATE IDLE If the Command field in the Input ControlCHECK_INPUT_(—) Register is for a Write/Load Input, and the NUM CommandComplete bit is a 0. INPUT_NUM_SOURCE_SEL=0 {SelectsUSER_INPUT_DATA_NUMBER as source} Else IDLE CHECK_INPUT_NUM If(INPUT_DATA_NUMBER>=10000) INVALID_INPUT If(INPUT_AUTO_LOCATION==INPUT_DATA_(—) NUMBER) Set the “Unused Input” bitin the INPUT_CONTROL_REG to a 0 to show that there is not an availableinput. This handles the case where the user has written to an autodetected input. Otherwise CALCULATE_PTR INVALID_INPUT Set an error bit,and assert an interrupt. Stop IDLE Processing at that point.CALCULATE_PTR INPUT_STRUCT_PTR= WAIT_FOR_WRITE INPUT_DATA_BASE+(INPUT_DATA_LENGTH/32+(1 if Remainder)+1)* INPUT_DATA_NUMBERINPUT_DATA_WORD_COUNT=0 {To route the write to the appropriateINPUT_REG_BANKn} WAIT_FOR_WRITE Set the I/O Ready bit to a 1 to signifythat the system is waiting for a write to the INPUT_STRUCT_VALUEregister. If a Write occurs to the STORE_INPUT INPUT_STRUCT_VALUEregister, the “Buffer Full” bit in the Input Control Register will beset. Set the I/O Ready bit to a 0 to signify that the Buffer is full andthat the system is not ready for a write. If the “Command” field of theInput Control IDLE Register is set to ‘111’ for a Reset Command, theuser wants to forcibly abandon the write. If no activity then the systemwill wait WAIT_FOR_WRITE STORE_INPUT Write the INPUT_STRUCT_VALUE to theINCREMENT_PTR location addressed by the INPUT_STRUCT_PTR. Clear the“Buffer Full” bit in the Input Control Register. Clear the “I/O Ready”bit in the Input Control Register. INCREMENT_PTR Add 1 to theINPUT_STRUCT_PTR CONDITION_PTR Add 1 to INPUT_DATA_WORD COUNTCONDITION_PTR If WRITE_MASK INPUT_STRUCT_PTR>=INPUT_DATA_BASE+(INPUT_DATA_LENGTH/32+(1 if Remainder)+1)* INPUT_DATA_NUMBER {Calculatethe Masking word to write in the next step}INPUT_STRUCT_VALUE[7:0]=PRESENT_MASK_(—) STEPINPUT_STRUCT_VALUE[15:8]=NEXT_MASK_(—) STEP Else WAIT_FOR_WRITEWRITE_MASK Write the value in INPUT_STRUCT_VALUE END_WRITE into thememory location pointed to by INPUT_STRUCT_PTR. END_WRITE Set the“Command Complete” bit in the Input ADD_INPUT_ALL_(—) Control Registerto a 1 to show that the EQ system has completed the write operation. Setthe “Calculate randomizer” Bit which will allow that process to getstarted. ADD_INPUT_ALL_EQ Process to map the Input Register for all ofSET_VALID the active equations, and to store the values in therandomizer Registers. SET_VALID The system needs to calculate theCALCULATE_OFFSET INPUT_STRUCT_PTR value that points to the correct Validword. INPUT_STRUCT_PTR= INPUT_VALID_BASE+ (USER_WRITE_INPUT_NUMBER/32)with no remainders. CALCULATE_OFFSET The sytstem needs to calculate theOffset CALCULATE_VALUE within the 32 bit word of the INPUT_VALID array.At the same time, the system needs to read the value of the presentINPUT_VALID array location. INPUT_VALID_ENCODE=INPUT_DATA_NUMBER-(INPUT_DATA_NUMBER/32) Read the location in DRAM pointed to byINPUT_STRUCT_PTR and store it in the INPUT_STRUCT_VALUE register.CALULATE_VALUE The INPUT_VALID_ENCODE value will be WRITE_VALUE appliedto a 5:32 decoder that produces a “1” in the desired location thatcorresponds to the input being written. This value will be OR-ed withthe value in INPUT_STRUCT_VALUE, and the result will be stored inINPUT_STRUCT_VALUE. WRITE_VALUE The value in INPUT_STRUCT_VALUE will beIDLE written to the memory location pointed to by INPUT_STRUCT_PTR.

TABLE CG USER_INPUT_WRITE - Process Description Process NameUSER_INPUT_WRITE Process Function This Process is called by the user towrite a new input into the system memory, but not have it loaded intothe Input Register and reflected in the Randomizer Tables. ReturnValue(s) Required Inputs USER_INPUT_DATA_NUMBER INPUT_STRUCT_VALUEPRESENT_MASK_STEP NEXT_MASK_STEP Modified Registers INPUT_STRUCT_PTR(This Process) INPUT_DATA_WORD_COUNT INPUT_CONTROL_REG—“Command”,“Buffer Full”, “Unused Input” and “I/O Ready” bits. INPUT_VALID_ENCODEModified Registers none (Sub-Processes) Error Conditions InvalidUSER_INPUT_DATA_NUMBER

TABLE CH USER_INPUT_WRITE - Process Implementation STATE NAME ACTIVITYNEXT STATE IDLE If the Command field in the Input ControlCHECK_INPUT_(—) Register is for a Write Input, and the NUM CommandComplete bit is a 0. INPUT_DATA_NUM_SOURCE=0 {Source isUSER_INPUT_DATA_NUMBER} Else IDLE CHECK_INPUT_NUM If(INPUT_DATA_NUMBER>=10000) INVALID_INPUT If(INPUT_AUTO_LOCATION==INPUT_DATA_(—) NUMBER) Set the “Unused Input” bitin the INPUT_CONTROL_REG to a 0 to show that there is not an availableinput. This handles the case where the user has written to an autodetected input. Otherwise CALCULATE_PTR INVALID_INPUT Set an error bit,and assert an interrupt. IDLE Stop Processing at that point.CALCULATE_PTR INPUT_STRUCT_PTR= WAIT_FOR_WRITE INPUT_DATA_BASE+(INPUT_DATA_LENGTH/32+(1 if Remainder)+1)* INPUT_DATA_NUMBER SetINPUT_DATA_WORD_COUNT=0 to signify that the system is pointing to thefirst part of the input word. WAIT_FOR_WRITE Set the I/O Ready bit to a1 to signify that the system is waiting for a write to theINPUT_STRUCT_VALUE register. If a Write occurs to the STORE_INPUTINPUT_STRUCT_VALUE register, the “Buffer Full” bit in the Input ControlRegister will be set. Set the I/O Ready bit to a 0 to signify that theBuffer is full and that the system is not ready for a write. If the“Command” field of the Input Control IDLE Register is set to ‘111’ for aReset Command, the user wants to forcibly abandon the write. If noactivity then the system will wait WAIT_FOR_WRITE STORE_INPUT Write theINPUT_STRUCT_VALUE to the INCREMENT_PTR location addressed by theINPUT_STRUCT_PTR. Clear the “Buffer Full” bit in the Input ControlRegister. Clear the “I/O Ready” bit in the Input Control Register.INCREMENT_PTR Add 1 to the INPUT_STRUCT_PTR CONDITION_PTR CONDITION_PTRIf WRITE_MASK INPUT_STRUCT_PTR>=INPUT_DATA_BASE+(INPUT_DATA_LENGTH/32+(1 if Remainder)+1)* INPUT_DATA_NUMBER {Calculatethe Masking word to write in the next step}INPUT_STRUCT_VALUE[7:0]=PRESENT_(—) MASK_STEPINPUT_STRUCT_VALUE[15:8]=NEXT_MASK_(—) STEP Else WAIT_FOR_WRITEWRITE_MASK Write the value in INPUT_STRUCT_VALUE END_WRITE into thememory location pointed to by INPUT_STRUCT_PTR. END_WRITE Set the“Command Complete” bit in the Input SET_VALID Control Register to a 1 toshow that the system has completed the write operation. Set the“Calculate randomizer” Bit which will allow that process to get started.SET_VALID The system needs to calculate the CALCULATE_OFFSETINPUT_STRUCT_PTR value that points to the correct Valid word.INPUT_STRUCT_PTR= INPUT_VALID_BASE+ (USER_WRITE_INPUT_NUMBER/32) with noremainders. CALCULATE_OFFSET The system needs to calculate the OffsetCALCULATE_VALUE within the 32 bit word of the INPUT_VALID array. At thesame time, the system needs to read the value of the present INPUT_VALIDarray location. INPUT_VALID_ENCODE=INPUT_DATA_NUMBER-(INPUT_DATA_NUMBER/32) Read the location in DRAM pointed to byINPUT_STRUCT_PTR and store it in the INPUT_STRUCT_VALUE register.CALULATE_VALUE The INPUT_VALID_ENCODE value will be WRITE_VALUE appliedto a 5:32 decoder that produces a “1” in the desired location thatcorresponds to the input being written. This value will be OR-ed withthe value in INPUT_STRUCT_VALUE, and the result will be stored inINPUT_STRUCT_VALUE. WRITE_VALUE The value in INPUT_STRUCT_VALUE willIDLE be written to the memory location pointed to by INPUT_STRUCT_PTR.

TABLE CI USER_INPUT_READ - Process Description Process NameUSER_INPUT_READ Process Function This Process is called by the user toread an input from DRAM. It does not load the value into the InputRegister. Return Value(s) INPUT_STRUCT_VALUE PRESENT_MASK_VALUENEXT_MASK_VALUE Required Inputs USER_INPUT_DATA_NUMBER ModifiedRegisters INPUT_STRUCT_PTR (This Process) INPUT_STRUCT_VALUEPRESENT_MASK_VALUE NEXT_MASK_VALUE INPUT_CONTROL_REG—“Command”, “CommandComplete” and “I/O Ready” bits. Modified Registers N/A (Sub-Processes)Error Conditions Invalid USER_INPUT_DATA_NUMBER

TABLE CJ USER_INPUT_READ Process Implementation STATE NAME ACTIVITY NEXTSTATE USER_INPUT_READ If the “Command” bits in the Input ControlCHECK_INPUT_(—) Register are for a “Read Input”, and the NUM “CommandComplete” bit is ==0. INPUT_DATA_NUM_SOURCE=0 {USER_INPUT_DATA_NUMBER isthe source} Else IDLE CHECK_INPUT_NUM The input number is stored in theINPUT_DATA_NUMBER register, and it needs to be verified as being a validinput. If (INPUT_DATA_NUMBER>=10000) INVALID_INPUT Else CALCULATE_PTRINVALID_INPUT Set an error bit, and assert an interrupt. Stop IDLEProcessing at that point. CALCULATE_PTR Calculate the Pointer intomemory: READ VALUE INPUT_STRUCT_PTR= INPUT_DATA_BASE+(INPUT_DATA_LENGTH/32+(1 if Remainder)+1)* INPUT_DATA_NUMBERINPUT_DATA_WORD_COUNT=0 READ_VALUE Read the value addressed by INCREMENTINPUT_STRUCT_PTR and place it into the INPUT_STRUCT_VALUE register.INCREMENT If there is a read to the CONDITION INPUT_STRUCT_VALUEregister, INPUT_STRUCT_PTR=INPUT_STRUCT_PTR+1 Else INCREMENT CONDITION{Check to see if the system has reached the READ_MASK MASK value. IfINPUT_STRUCT_PTR==(INPUT_DATA_BASE+ (INPUT_DATA_LENGTH/32+(1 ifRemainder)))* INPUT_DATA_NUMBER Otherwise READ_VALUE READ_MASK Read thevalue addressed by FINISH_READ INPUT_STRUCT_PTR. Bits[7:0] of the valuebeing read should be directed to the PRESENT_MASK_VALUE register.Bits[15:8] of the value being read should be directed to theNEXT_MASK_VALUE register. FINISH_READ Set the “Command Complete” bit inthe Input IDLE Control Register.

TABLE CK USER_INPUT_CLEAR - Process Description Process NameUSER_INPUT_CLEAR Process Function This Process is called by the user toremove an Input from the system. The process loads the input into theInput Register so that it can be taken out of all the equation mappings.In addition, it clears the Input Valid bit. Return Value(s)INPUT_CONTROL_REG—“Command Complete” Required InputsUSER_INPUT_DATA_NUMBER Modified Registers INPUT_STRUCT_PTR (ThisProcess) INPUT_STRUCT_VALUE INPUT_DATA_WORD_COUNT PRESENT_MASK_STEPNEXT_MASK_STEP INPUT_CONTROL_REG—“Command”, “Command Complete” and “I/OReady” bits. Modified Registers SUBTRACT_INPUT_ALL_EQ (Sub-Processes)Error Conditions Invalid USER_INPUT_DATA_NUMBER

TABLE CL USER_INPUT_CLEAR - Process Implementation STATE NAME ACTIVITYNEXT STATE USER_INPUT_CLEAR If the “Command” bits in the Input ControlCHECK_INPUT_NUM Register are for a “Read Input”, and the “CommandComplete” bit is ==0. INPUT_DATA_NUM_SOURCE=0 {Source is theUSER_INPUT_DATA_NUMBER} Else IDLE CHECK_INPUT_NUM The input number isstored in the INPUT_DATA_NUMBER register, and it needs to be verified asbeing a valid input. If (INPUT_DATA_NUMBER>=10000) INVALID_INPUT ElseCALCULATE_PTR INVALID_INPUT Set an error bit, and assert an interrupt.IDLE Stop Processing at that point. CALCULATE_PTR Calculate the Pointerinto memory: READ VALUE INPUT_STRUCT_PTR= INPUT_DATA_BASE+(INPUT_DATA_LENGTH/32+(1 if Remainder)+1)* INPUT_DATA_NUMBER SetINPUT_DATA_WORD_COUNT=0 READ_VALUE Read the value addressed by INCREMENTINPUT_STRUCT_PTR and place it into the INPUT_REG_BANKn that is selectedby the INPUT_DATA_WORD_COUNT. INCREMENTINPUT_STRUCT_PTR=INPUT_STRUCT_(—) CONDITION PTR+1 CONDITION {Check tosee if the system has reached READ_MASK the MASK value. IfINPUT_STRUCT_PTR==(INPUT_DATA_BASE+ (INPUT_DATA_LENGTH/32+(1 ifRemainder)))* INPUT_DATA_NUMBER Otherwise READ_VALUE READ_MASK Read thevalue addressed by SUBTRACT_INPUT_(—) INPUT_STRUCT_PTR. Bits[7:0] of theALL_EQ value being read should be directed to the PRESENT_MASK_STEPregister. Bits[15:8] of the value being read should be directed to theNEXT_MASK_STEP register. SUBTRACT_INPUT_ALL_EQ This Process removes theinput in the Input CLEAR_VALID Register from all of the equation Maps.CLEAR_VALID Calculate the Offset into the INPUT_VALID GET_VALID_WORDarray for the value that is encoded here. INPUT_STRUCT_PTR=INPUT_VALID_BASE+ INT(INPUT_DATA_NUMBER/32) GET_VALID_WORD Read thevalue pointed to by GENERATE_NEW_(—) INPUT_STRUCT_PTR, and write it intothe VALID INPUT_STRUCT_VALUE register. GENERATE_NEW_VALID TakeINPUT_DATA_NUMBER[4:0] and WRITE_VALID_BACK apply it to a 5 to 32decoder. And the Inverse of this operation with INPUT_STRUCT_VALUE andstore the result in INPUT_STRUCT_VALUE. {This clears out the bit that isselected.} WRITE_VALID_BACK Write INPUT_STRUCT_VALUE into the IDLElocation pointed to by INPUT_STRUCT_PTR. INVALID_CLEAR An ErrorInterrupt will be generated for an IDLE Invalid Input Clear that is outof range.

TABLE CM SYS_INPUT_LOAD - Process Description Process NameSYS_INPUT_LOAD Process Function This Process is called by the system toretrieve an input value from DRAM and load it into the Input Register.Return Value(s) INPUT_CONTROL_REG—“Command Complete” Required InputsSYS_INPUT_DATA_NUMBER Modified Registers INPUT_STRUCT_PTR (This Process)INPUT_STRUCT_VALUE INPUT_DATA_WORD_COUNT PRESENT_MASK_STEPNEXT_MASK_STEP INPUT_CONTROL_REG—“Command”, “Command Complete” and “I/OReady” bits. Modified Registers (Sub-Processes) Error Conditions None

TABLE CN SYS_INPUT_LOAD - Process Implementation STATE NAME ACTIVITYNEXT STATE USER_INPUT_CLEAR Driven by the System CALCULATE_PTRINPUT_DATA_NUM_SOURCE=1 {Source is the SYS_INPUT_DATA_NUMBER} Else IDLECALCULATE_PTR Calculate the Pointer into memory: READ VALUEINPUT_STRUCT_PTR= INPUT_DATA_BASE+ (INPUT_DATA_LENGTH/32+(1 ifRemainder)+1)* INPUT_DATA_NUMBER Set INPUT_DATA_WORD_COUNT=0 READ_VALUERead the value addressed by INCREMENT INPUT_STRUCT_PTR and place it intothe INPUT_REG_BANKn that is selected by the INPUT_DATA_WORD_COUNT.INCREMENT INPUT_STRUCT_PTR=INPUT_STRUCT_PTR+1 CONDITION CONDITION {Checkto see if the system has reached the READ_MASK MASK value. IfINPUT_STRUCT_PTR==(INPUT_DATA_BASE+ (INPUT_DATA_LENGTH/32+(1 ifRemainder)))* INPUT_DATA_NUMBER Otherwise READ_VALUE READ_MASK Read thevalue addressed by IDLE INPUT_STRUCT_PTR. Bits[7:0] of the value beingread should be directed to the PRESENT_MASK_STEP register. Bits[15:8] ofthe value being read should be directed to the NEXT_MASK_STEP register.Set a bit to signify that this process is complete.State Machines for the “1024 Bit Input Register” Block

There are no state machines dedicated to this block.

State Machines for the “Masking and Enabling Logic” Block

The following state machines are used to manage the masking and enablingfunctions of the system (see Table CO-CR below).

TABLE CO INIT_FORCED_MASK - Process Description Process NameINIT_FORCED_MASK Process Function This is a system process is used tosetup all bits that will be masked off from use in the RandomizerCalculations. This includes all ON/OFF bits as well as bits after theuser programmed INPUT_DATA_LENGTH. Return Value(s) Required InputsMASK_OFF_CYCLE_REG, MASK_ON_CYCLE_REG Modified Registers SET_ENAB_BANK(This Process) SET_ENAB_BIT FORCE_MASK_ON Modified Registers(Sub-Processes) Error Conditions

TABLE CP INIT_FORCED_MASK - Process Implementation STATE NAME ACTIVITYNEXT STATE IDLE If the Main Control Directs this process toINITIALIZE_VALUES start. Done after a change to INPUT_DATA_LENGTH,MASK_ON_CYCLE_REG or MASK_OFF_CYCLE_REG. Else IDLE INITIALIZE_VALUES Setthe following registers: QUALIFY_BANK SET_ENAB_BANK=0 SET_ENAB_BIT=0SET_ENAB_FROM_SMS0=0 FORCE_MASK_ON=0 QUALIFY_BANK Here is where thesystem determines PROG_MASK0 whether this BANK is covered by one of thefour user programmable MASK Registers If (ENAB_BANK==MASK_REGISTER_0) &&(MASK_REGISTER_0 Enable Bit==1) Else If PROG_MASK1(ENAB_BANK==MASK_REGISTER_1) && (MASK_REGISTER_1 Enable Bit==1) Else IfPROG_MASK2 (ENAB_BANK==MASK_REGISTER_2) && (MASK_REGISTER_2 EnableBit==1) Else If PROG_MASK3 (ENAB_BANK==MASK_REGISTER_3) &&(MASK_REGISTER_3 Enable Bit==1) Else USE_ON_OFF PROG_MASK0SET_ENAB_FROM_SMS0=1 FORCED_MASK_(—) SET_ENAB_SMSO_SELECT=0 OFFPROG_MASK1 SET_ENAB_FROM_SMS0=1 FORCED_MASK_(—) SET_ENAB_SMSO_SELECT=1OFF PROG_MASK2 SET_ENAB_FROM_SMS0=1 FORCED_MASK_(—)SET_ENAB_SMSO_SELECT=2 OFF PROG_MASK3 SET_ENAB_FROM_SMS0=1FORCED_MASK_(—) SET_ENAB_SMSO_SELECT=3 OFF USE_ON_OFFSET_ENAB_FROM_SMS0=0 QUALIFY_BIT QUALIFY_BIT The SET_ENAB_BANK andFORCED_MASK_(—) SET_ENAB_BIT values need to be OFF combined to generatethe input bit number. Check to see if this bit is the bit where thesystem is supposed to start MASKING OFF the data. IF (((SET_ENAB_BANK<<5) ∥ (SET_ENAB_BIT)) == MASK_OFF_CYCLE_REG) && (MASK_OFF_CYCLE_REGEnable = 1) Check to see if this bit is the bit where theFORCED_MASK_(—) system is supposed to start MASKING ON ON the data. IF(((SET_ENAB_BANK <<5) ∥ (SET_ENAB_BIT)) == MASK_ON_CYCLE_REG) &&(MASK_ON_CYCLE_REG Enable = 1) Check to see if this bit is the end ofthe FORCED_MASK_(—) INPUT_DATA_LENGTH. ON IF (((SET_ENAB_BANK <<5) ∥(SET_ENAB_BIT)) == INPUT_DATA_LENGTH) FORCED_MASK_OFF Set theFORCE_MASK_ON bit to “0” to USE_FORCE_STATUS signify that the system isnot masking all bits at this point. FORCED_MASK_ON Set the FORCE_MASK_ONbit to “1” to USE_FORCE_STATUS signify that all bits will be masked forthe time being. USE_FORCE_STATUS Write_Bit=FORCE_MASK_ON WRITE_ENAB_(—)BIT WRITE_ENAB_BIT The SET_ENAB_BANK and INCREMENT_BIT SET_ENAB_BIT needto be concatenated and run through two 10 to 1024 decoder. One set ofdecoder outputs will drive the Set lines on the Enable bits, and one setof decoder outputs will drive the Reset lines on the Enable Bits. If theWrite_Bit=0 then the system needs to enable the Set line, and if theWrite_Bit=1 then the system needsto enable the Reset line. INCREMENT_BITSET_ENAB_BIT=SET_ENAB_BIT+1. If Rollover INCREMENT_BANK Else QUALIFY_BITINCREMENT_BANK SET_ENAB_BANK=SET_ENAB_BANK+1 If Rollover IDLE ElseQUALIFY_BANK

TABLE CQ INIT_PROG_MASK - Process Description Process NameINIT_PROG_MASK Process Function This is a system process to setup all ofthe Programmable Masking Impact Bits for the system. Return Value(s)Required Inputs MASK_OFF_CYCLE_REG, MASK_ON_CYCLE_REG Modified RegistersSET_ENAB_BANK (This Process) SET_ENAB_BIT INPUT_SOURCE_SELECTEQUATION_STORE_ENTRY SET_ENAB_SMSO_SELECT WALKING_ONE_VALUE ModifiedRegisters N/A (Sub-Processes) Error Conditions none

TABLE CR INIT_PROG_MASK - Process Implementation STATE NAME ACTIVITYNEXT STATE IDLE If the Main Control Directs this process toINITIALIZE_VALUES start. {Done on initialization or after an equation isswapped out} Else IDLE INITIALIZE_VALUES Set the following registers:QUALIFY_BANK SET_ENAB_BANK=0 INPUT_SOURCE_SELECT=1 {Selects WalkingOne's} QUALIFY_BANK Here is where the system determines CHECK_MASK0whether this BANK is covered by one of the four user programmable MASKRegisters Set EQUATION_STORE_ENTRY=0 If(SET_ENAB_BANK==MASK_REGISTER_(—) 0) && (MASK_REGISTER_0 Enable Bit==1)Else If CHECK_MASK1 (SET_ENAB_BANK==MASK_REGISTER_(—) 1) &&(MASK_REGISTER_1 Enable Bit==1) Else If CHECK_MASK2(SET_ENAB_BANK==MASK_REGISTER_(—) 2) && (MASK_REGISTER_2 Enable Bit==1)Else If CHECK_MASK3 (SET_ENAB_BANK==MASK_REGISTER_(—) 3) &&(MASK_REGISTER_3 Enable Bit==1) Else INCREMENT_BANK CHECK_MASK0SET_ENAB_SMSO_SELECT=0 SET_WALKING_ONES SET_ENAB_BIT=0 CHECK_MASK1SET_ENAB_SMSO_SELECT=1 SET_WALKING_ONES SET_ENAB_BIT=0 CHECK_MASK2SET_ENAB_SMSO_SELECT=2 SET_WALKING_ONES SET_ENAB_BIT=0 CHECK_MASK3SET_ENAB_SMSO_SELECT=3 SET_WALKING_ONES SET_ENAB_BIT=0 SET_WALKING_ONESWALKING_ONE_VALUE=(SET_ENAB_BANK<<5)| MAP_VALUE (SET_ENAB_BIT) MAP_VALUEWrite the Mapper Output into the Mask INCREMENT_BIT Impact registerassociated with Equation Number= EQUATION_STORE_ENTRY, MaskRegister=SET_ENAB_SMS0_SELECT, and Bit Number=SET_ENAB_BIT.INCREMENT_BIT SET_ENAB_BIT=SET_ENAB_BIT+1 If Overflow INCREMENT_EQ ElseSET_WALKING_ONES INCREMENT_EQ EQUATION_STORE_ENTRY=EQUATION_STORE_ENTRY+1 If Overflow INCREMENT_BANK Else SET_WALKING_ONESINCREMENT_BANK SET_ENAB_BANK=SET_ENAB_BANK+1 If Overflow IDLE ElseQUALIFY_BANKState Machines for the “Equation Mapper” Block

There are no state machines specific to this block.

State Machines for the “Mapper Multiplexer” Block

There are no state machines specific to this block.

State Machines for the “Mapper Storage Control and Storage StateMachine” Blk

The following processes have to do with initializing, storing, andremoving and matching values in a primary randomizer table (see TablesCS-DV below).

TABLE CS RAND_INIT - Process Description Process Name RAND_INIT ProcessFunction This process is used to initialize and clear out a randomizerTable for one specific equation. Only the first entry of each 2 × 16 bitprimary randomizer entry must be cleared in the main table. In addition,the Valid Multiple Table must be cleared out for the equation to showthat none of the Multiple entries are being used. Return Value(s)Required Inputs RAND_INIT_EQ Modified Registers RAND_INIT_VALUE (ThisProcess) RAND_INIT_ADDRESS RAND_INIT_COUNT Modified Registers N/A(Sub-Processes) Error Conditions none

TABLE CT RAND_INIT - Process Description STATE NAME ACTIVITY NEXT STATECLEAR_EQUATION If the Main Control Directs this INITIALIZE process tostart. The Main Control will set “RAND_INIT_EQ” to the number of theequation that is being initialized. Else CLEAR_EQUATION INITIALIZE SetRAND_INIT_VALUE=0 CLEAR_VALUE Set RAND_INIT_ADDRESS=PRIM_RAND_TABLE_BASE+ RAND_INIT_EQ*PRIM_RAND_LENGTH {This sets up thepointer to point to the base of the structure} Set RAND_INIT_COUNT=0{This sets up that the sytstem has not cleared any locations yet}CLEAR_VALUE Write RAND_INIT_VALUE to the location pointed to byRAND_INIT_ADDRESS RAND_INIT_ADDRESS=RAND_INIT_(—) ADDRESS+2. IfRAND_INIT_COUNT==65535 END_RAND_TABLE RAND_INIT_COUNT++ {At end ofcycle} Else CLEAR_VALUE RAND_INIT_COUNT++ {At end of cycle}END_RAND_TABLE RAND_INIT_COUNT=0 GET_MULT_ADDRESS GET_MULT_ADDRESS SetRAND_INIT_ADDRESS= CLEAR_MULT PRIM_RAND_TABLE_BASE+RAND_INIT_EQ*PRIM_RAND_LENGTH+ MULT_VALID_OFFSET {This sets up thepointer to point to the base of the Multiple Structure}RAND_INIT_COUNT=0 CLEAR_MULT Write RAND_INIT_VALUE to the locationpointed to by RAND_INIT_ADDRESS RAND_INIT_ADDRESS++ IfRAND_INIT_COUNT==67 {End of IDLE Cycle} Else CLEAR_MULTRAND_INIT_COUNT++ {After Cycle}

TABLE CU PRAND_ADD_ENTRY - Process Description Process NamePRAND_ADD_ENTRY Process Function This process is used to add arandomizer Table Entry for a single equation. Return Value(s) (Needsomething to indicate completion) Required Inputs PRIM_RAND_TABLE_BASEPRIM_RAND_EQ_NUM PRIM_RAND_LENGTH INPUT_DATA_NUMBER NEXT_MASK_STEPPRIM_RAND_VALUE SEC_RAND_VALUE Modified Registers PRIM_RAND_LOCATION(This Process) PRIM_RAND_ENTRY TEMP_POINTER0 TEMP_VALUE0 ModifiedRegisters GET_NEW_MULT_ENTRY returns (Sub-Processes) TEMP_COUNT ErrorConditions none

TABLE CV PRAND_ADD_ENTRY - Process Implementation STATE NAME ACTIVITYNEXT STATE PRAND_ADD_ENTRY A process to process handshake startsSTART_PROCESS this off. Otherwise PRAND_ADD_ENTRY START_PROCESS Thesystem needs to generate the GET_PRIOR_ENTRY pointer into the primaryrandomizer Table that will be used for this value. PRIM_RAND_LOCATION =PRIM_RAND_TABLE_BASE+ PRIM_RAND_EQ_NUM*PRIM_RAND_(—) LENGTH+2*PRIM_RAND_VALUE GET_PRIOR_ENTRY Get the value from SRAM that isEVALUATE_PRIOR pointed to by PRIM_RAND_LOCATION, and store it inPRIM_RAND_ENTRY. EVALUATE_PRIOR Evaluate B15, B14, B13, B12 to see whatthe previous entry consisted of. If B15=0, B14=0 (No Existing Entry)NEW_SINGLE_ENTRY If B15=0, B14=1 (Existing Single Entry) NEW_PAIR_ENTRYIf B15=1, B14=0 (Existing Pair Entry) NEW_TRIPLE_ENTRY If B15=1, B14=1,B13=0, B12=0 NEW_QUAD_ENTRY (Existing Triple Entry) If B15=1, B14=1,B13=0, B12=1 NEW_OVERFLOW_ENTRY (Existing Quad Entry) If B15=1, B14=1,B13=1, B12=0 ADDED_OVERFLOW (Existing Overflow Entry) If B15=1, B14=1,B13=1, B12=1 (Single NEW_PAIR_ENTRY Mask Entry)

TABLE CW Path for a New Single Entry NEW_SINGLE_ENTRY IfNEXT_MASK_STEP!=0 (Masking STORE_SINGLE_ENTRY Step) Bits[15:12]=’1111’.Bits[4:0]=NEXT_MASK_STEP Store Bits[15:0] in PRIM_RAND_ENTRY IfNEXT_MASK_STEP=0 (Non-Masking Step) Bits[15:14]=’01’Bits[13:0]=INPUT_DATA_NUMBER Store Bits[15:0] in PRIM_RAND_ENTRYSTORE_SINGLE_ENTRY Write the PRIM_RAND_ENTRY into the STORE_SING_SEC_(—)memory pointed to by the RAN PRIM_RAND_LOCATION pointer.PRIM_RAND_LOCATION++ STORE_SING_SEC_RAN Write the SEC_RAND_VALUE intothe PRAND_ADD_ENTRY memory pointed to by the PRIM_RAND_LOCATION pointer.

TABLE CX Path for handling a New Pair NEW_PAIR_ENTRY GET_NEW_MULT_ENTRYCALC_NEW_MULT_(—) (Macro Call) PTR Return value of pair index inTEMP_COUNT. CALC_NEW_MULT_PTR TEMP_POINTER0= COPY_SINGLE_INPUTPRIM_RAND_TABLE_BASE+ PRIM_RAND_EQ_NUM*PRIM_RAND_(—) LENGTH+MULT_TABLE_OFFSET+ TEMP_COUNT*8 COPY_SINGLE_INPUT PRIM_RAND_ENTRYcontains either GET_PRIM_RAND_SEC the input value or a Masking Value. Itneeds to be copied over into the pair structure as the First Value InputPointer. Write PRIM_RAND_ENTRY into location (TEMP_POINTER0+4)GET_PRIM_RAND_SEC Get the information that is stored at theSTORE_PRIM_RAND_(—) location pointed to by SEC (PRIM_RAND_LOCATION+1),and store it in PRIM_RAND_ENTRY. STORE_PRIM_RAND_SEC PRIM_RAND_ENTRY nowholds the STORE_SINGLE_SEC secondary randomizer value. PRIM_RAND_ENTRYshould be stored in location TEMP_POINTER0. {This calculation is beingdone early when the ALU's are not being utilized} Calculate the valuefor the New Pair Entry in the primary randomizer Table. The Pair Indexis stored in TEMP_COUNT, and the system needs to modify the upper bits.PRIM_RAND_ENTRY[15:14]=’10’ PRIM_RAND_ENTRY[13:0]=TEMP_COUNT [13:0]STORE_SINGLE_SEC Store the SEC_RAND_VALUE for the STORE_NEW_INPUT latestinput in the location TEMP_POINTER0+1. Calculate the pair table valuefor the new input. If NEXT_MASK_STEP!=0(Masking Step)TEMP_VALUE0[15]=’1’. TEMP_VALUE0[4:0]=NEXT_MASK_STEP If NEXT_MASK_STEP=0(Non-Masking Step) TEMP_VALUE0[15]=’0’TEMP_VALUE0[13:0]=INPUT_DATA_NUMBER STORE_NEW_INPUT Store Bits[15:0] inthe location pointed STORE_PRIM_ENTRY_(—) to by TEMP_POINTER0+5. PAIRSTORE_PRIM_ENTRY_PAIR Write PRIM_RAND_ENTRY into the PRAND_ADD_ENTRYlocation pointed to by PRIM_RAND_LOCATION. This will activate the newMultiple Entry block.

TABLE CY Path For a New Triple NEW_TRIPLE TEMP_POINTER0 will be used toWRITE_THIRD_SR access the Multiple Entry Table. TEMP_POINTER0=PRIM_RAND_TABLE_BASE+ PRIM_RAND_EQ_NUM*PRIM_RAND_(—) LENGTH+MULT_TABLE_OFFSET+PRIM_RAND_(—) ENTRY[9:0]*8 WRITE_THIRD_SR Write theSEC_RAND_VALUE into the WRITE_THIRD_INPUT location pointed to by(TEMP_POINTER0+2). This writes the Third Input secondary randomizervalue into the Multiple Entry table. {Calculate the new THIRD_INPUTvalue for the Multiple Entry Table.} If NEXT_MASK_STEP!=0,TEMP_VALUE0[15]=1. TEMP_VALUE0[4:0]=NEXT_MASK_STEP If NEXT_MASK_STEP=0,TEMP_VALUE0[15]=0. TEMP_VALUE0[13:0]=PRIM_RAND_INPUT. WRITE_THIRD_INPUTWrite TEMP_VALUE0 (previously WRITE_PRIM_RAND_(—) calculated) into thelocation pointed to TRIP by (TEMP_POINTER0+6). This loads the Thirdinput into the Multiple Entry Table. {Calculate the new PRIM_RAND_ENTRYvalue that signifies that the system is dealing with a Triple, and saveit for the end of this routine} PRIM_RAND_ENTRY[15:12]=‘1100’PRIM_RAND_ENTRY[9:0]=PRIM_RAND_(—) ENTRY[9:0] WRITE_PRIM_RAND_TRIP WritePRIM_RAND_ENTRY (previously PRAND_ADD_ENTRY calculated) into thelocation pointed to by PRIM_RAND_LOCATION to setup and activate the NewTriple.

TABLE CZ Path For a New quadruple NEW_QUAD_ENTRY TEMP_POINTER0 will beused to access WRITE_FOURTH_SR the Multiple Entry Table. TEMP_POINTER0=PRIM_RAND_TABLE_BASE+ PRIM_RAND_EQ_NUM*PRIM_RAND_LENGTH+MULT_TABLE_OFFSET+PRIM_RAND_ENTRY [9:0]*8 WRITE_FOURTH_SR Write theSEC_RAND_VALUE into the WRITE_FOURTH_INPUT location pointed to by(TEMP_POINTER0+3). This writes the Third Fourth Input secondaryrandomizer value into the Multiple Entry table. {Calculate the newFOURTH_INPUT value for the Multiple Entry Table.} If NEXT_MASK_STEP!=0,TEMP_VALUE0[15]=1. TEMP_VALUE0[4:0]=NEXT_MASK_STEP If NEXT_MASK_STEP=0,TEMP_VALUE0[15]=0. TEMP_VALUE0[13:0]=PRIM_RAND_INPUT. WRITE_FOURTH_INPUTWrite TEMP_VALUE0 (previously WRITE_PRIM_RAND_(—) calculated) into thelocation pointed to by QUAD (TEMP_POINTER0+7). This loads the Fourthinput into the Multiple Entry Table. {Calculate the new PRIM_RAND_ENTRYvalue that signifies that the system is dealing with a quadruple, andsave it for the end of this routine} PRIM_RAND_ENTRY[15:12]=’1101’PRIM_RAND_ENTRY[4:0]=TEMP_VALUE0 [4:0] WRITE_PRIM_RAND_QUAD WritePRIM_RAND_ENTRY (previously PRAND_ADD_ENTRY calculated) into thelocation pointed to by PRIM_RAND_LOCATION to setup and activate the Newquadruple.

TABLE DA Path for a New Overflow Entry NEW_OVERFLOW_ENTRY At this point,the system has a Multiple CALC_FIRST_OVERFLOW Entry (quadruple ) that itneeds to add an input to. PRIM_RAND_ENTRY[9:0] contains the number forthe Multiple Entry Location. TEMP_POINTER0= PRIM_RAND_TABLE_BASE+PRIM_RAND_EQ_NUM*PRIM_RAND_LENGTH+ MULT_TABLE_OFFSET+(PRIM_RAND_ENTRY[9:0])*8 CALC_FIRST_OVERFLOW If NEXT_MASK_STEP!=0{Masking} WR_FIRST_OVER_INPUT TEMP_VALUE0[15]=1TEMP_VALUE0[4:0]=NEXT_MASK_STEP If NEXT_MASK_STEP=0 {Non Masking}TEMP_VALUE0[15]=0 TEMP_VALUE0[13:0]=INPUT_DATA_NUMBERWR_FIRST_OVER_INPUT Write TEMP_VALUE0 into the locationWRITE_PRIM_OVERFLOW pointed to by TEMP_POINTER0+0. {This is normally thefirst secondary randomizer Value} {Calculate the new PRIM_RAND_ENTRY toshow that there is a single overflow.}PRIM_RAND_ENTRY[9:0]=PRIM_RAND_(—) ENTRY[9:0]PRIM_RAND_ENTRY[15:10]=‘111001’ The ‘01’ in bits 10,11 map to a singleoverflow. WRITE_PRIM_OVERFLOW Write the PRIM_RAND_ENTRY to thePRAND_ADD_ENTRY location pointed to by the PRIM_RAND_LOCATION pointer.

TABLE DB Path for an Added Overflow Entry ADDED_OVERFLOW_ENTRY At thispoint, the system has a Multiple CHECK_OVERFLOW_NUM Entry Overflow thatit needs to add an input to. PRIM_RAND_ENTRY[9:0] contains the numberfor the Multiple Entry Location. TEMP_POINTER0= PRIM_RAND_TABLE_BASE+PRIM_RAND_EQ_NUM*PRIM_RAND_LENGTH+ MULT_TABLE_OFFSET+(PRIM_RAND_ENTRY[9:0])*8 CHECK_OVERFLOW_NUM {The following is done tocalculate the value of the new input that is to be stored} IfNEXT_MASK_STEP!=0{Masking} TEMP_VALUE0[15]=1TEMP_VALUE0[4:0]=NEXT_MASK_STEP If NEXT_MASK_STEP=0 {Non Masking}TEMP_VALUE0[15]=0 TEMP_VALUE0[13:0]=INPUT_DATA_NUMBER IfPRIM_RAND_ENTRY[11:10]=’01’ {1 WR_SEC_OVERFLOW Over Exists} IfPRIM_RAND_ENTRY[11:10]=’10’ {2 WR_THIRD_OVERFLOW Over Exists} IfPRIM_RAND_ENTRY[11:10]=’11’ {3 WR_FOURTH_OVERFLOW Over Exists} IfPRIM_RAND_ENTRY[11:10]=’00’ {4 WR_OVER_ERROR Over Exists}WR_SEC_OVERFLOW Write TEMP_VALUE0 into the location WRITE_PRIM_OVERFLOWpointed to by TEMP_POINTER0+1. {This is normally the second secondaryrandomizer Value} {Calculate the new PRIM_RAND_ENTRY to show that thereare two overflow.} PRIM_RAND_ENTRY[9:0]=PRIM_RAND_(—) ENTRY[9:0]PRIM_RAND_ENTRY[15:10]=’111010’ The ‘10’ in bits 11,10 map to a doubleoverflow. WR_THIRD_OVERFLOW Write TEMP_VALUE0 into the locationWRITE_PRIM_OVERFLOW pointed to by TEMP_POINTER0+2. {This is normally thethird secondary randomizer Value} {Calculate the new PRIM_RAND_ENTRY toshow that there are three overflow.} PRIM_RAND_ENTRY[9:0]=PRIM_RAND_(—)ENTRY[9:0] PRIM_RAND_ENTRY[15:10]=‘111011’ The ‘11’ in bits 11,10 map toa triple overflow. WR_FOURTH_OVERFLOW Write TEMP_VALUE0 into thelocation WRITE_PRIM_OVERFLOW pointed to by TEMP_POINTER0+3. {This isnormally the fourth secondary randomizer Value} {Calculate the newPRIM_RAND_ENTRY to show that there are four overflow.}PRIM_RAND_ENTRY[9:0]=PRIM_RAND_(—) ENTRY[9:0]PRIM_RAND_ENTRY[15:10]=’111000’ The ‘00’ in bits 11,10 map to aquadruple overflow. WR_OVER_ERROR Fire off an interrupt and set a statusPRAND_ADD_ENTRY register to show that the system has overflowed aMultiple Entry. WRITE_PRIM_OVERFLOW Write the PRIM_RAND_ENTRY to thePRAND_ADD_ENTRY location pointed to by the PRIM_RAND_LOCATION pointer.

TABLE DC GET_NEW_MULT_ENTRY - Process Description Process NameGET_NEW_MULT_ENTRY Process Function This Process is called to searchthrough the Multiple Entry Structure and to find and tag a specificMultiple Entry as being used, and to provide the index to the MultipleEntry. Return Value(s) TEMP_COUNT {Multiple Entry Index} Required InputsPRIM_RAND_EQ_NUM PRIM_RAND_TABLE_BASE PRIM_RAND_LENGTH MULT_VALID_OFFSETModified Registers TEMP_POINTER0 (This Process) TEMP_POINTER1TEMP_VALUE0 TEMP_VALUE1 TEMP_ENCODE0 TEMP_ENCODE1 TEMP_COUNT ModifiedRegisters N/A (Sub-Processes) Error Conditions none

TABLE DE GET_NEW_MULT_ENTRY - Process Implementation GET_NEW_MULT_ENTRYCalculate the location for the first READ_MULT_SUP_BLOCK multiple entrysuper block entry. TEMP_POINTER0= PRIM_RAND_TABLE_BASE+PRIM_RAND_EQ_NUM*PRIM_RAND_(—) LENGTH+ MULT_VALID_OFFSET+64 SetTEMP_COUNT=0 to signify that the sytstem is looking at the FirstMultiple Entry Super Block. READ_MULT_SUP_BLOCK Read the value pointedto by CHECK_AVAIL_SUP_BLOCK TEMP_POINTER0, and store it in theTEMP_VALUE0 location. CHECK_AVAIL_SUP_BLOCK Run the TEMP_VALUE0 througha 16 bit priority encoder to report back the lowest location with a 0.TEMP_ENCODE0=(5 Bit Encoded Version from 0–15, with 16 being a noun-used value location.) If TEMP_ENCODE0[4]=0 CALC_SUB_BLOCK_PTR IfTEMP_ENCODE0[4]=1 and INCREMENT_SUP_BLOCK TEMP_COUNT<3 IfTEMP_ENCODE0[4]=1 and FIND_MULT_ERROR TEMP_COUNT>=3 INCREMENT_SUP_BLOCKTEMP_COUNT=TEMP_COUNT+1 READ_MULT_SUP_BLOCKTEMP_POINTER0=TEMP_POINTER0+1 CALC_SUB_BLOCK_PTR TEMP_POINTER1 will nowbe set to READ_MULT_SUB_BLOCK point to the sub-block location thatstores information regarding 16 pair entries. TEMP_POINTER1=PRIM_RAND_TABLE_BASE+ PRIME_RAND_EQ_NUM*PRIM_RAND_(—) LENGTH+MULT_VALID_OFFSET+ TEMP_COUNT*16+TEMP_ENCODE0[ 3:0] READ_MULT_SUB_BLOCKCalculate upper 6 bits of the 10 bit GET_MULT_LOCATION Multiple EntryIndex, and store them in TEMP_COUNT: TEMP_COUNT=(TEMP_COUNT*16+TEMP_ENCODE0[3:0]) <<4 The value stored at the location pointed to byTEMP_POINTER1 should be placed in TEMP_VALUE1 GET_MULT_LOCATION RunTEMP_VALUE1 through a 16 bit priority encoder to report back the lowestlocation with a 0. TEMP_ENCODE1=(5 Bit Encoded Version from 0–15, with16 being a no un-used value location.) If TEMP_ENCODE1[4]=0 {There is anCALC_MULT_USED un-used pair} If TEMP_ENCODE1[4]=1 {There are noFIND_MULT_ERROR un-used multiple entry locations, and something has gonewrong with the system} CALC_MULT_USED This section is used to calculatethe STORE_MULT_USED new multiple entry index to return to the user.TEMP_COUNT=TEMP_COUNT+TEMP_(—) ENCODE1[3:0] Run TEMP_ENCODE1[3:0]through a 4 bit decoder to differentiate the location which is beingused. OR this value with TEMP_VALUE1 and store it back into TEMP_VALUE1.STORE_MULT_USED Write TEMP_VALUE1 to the location CHECK_SUPERBLOCKpointed to by TEMP_POINTER1. CHECK_SUPERBLOCK The TEMP_VALUE1 needs tobe checked to see whether there are any available locations remaining.If there are not any, then the Upper BLOCK needs to be modified. RunTEMP_VALUE1 through a 16 bit priority encoder to report back the lowestlocation with a 0. TEMP_ENCODE1=(5 Bit Encoded Version from 0–15, with16 being a no un-used value location.) If TEMP_ENCODE1[4]=0 {UnusedCALC_MULT_PTR locations remain} If TEMP_ENCODE1[4]=1 {No UnusedCALC_MULT_SUPER_BLOCK locations remain} CALC_MULT_SUPERBLOCK At thispoint, the sub-block of 16 CLEAR_MULT_SUPER_BLOCK multiple entries isfull. Therefore the bit in the super-block needs to be set to signifythat there is no room for that sub-block. Run TEMP_ENCODE0[3:0] througha 4 bit decoder to differentiate the location which is being used. ORthis value with TEMP_VALUE0. CLEAR_MULT_SUPERBLOCK Write TEMP_VALUE0into the location FM_IDLE pointed to by the TEMP_POINTER0 pointer. Thismodifies the super-block to indicate that all of the sub-blocks areused. FIND_MULT_ERROR There has been an error in trying to find FM_IDLEan available multiple entry. This will be set in a status register, andthen the system will interrupt that there is an error.

TABLE DF PRAND_SUB_ENTRY - Process Description Process NamePRAND_SUB_ENTRY Process Function This process is used to remove an entryfrom a primary randomizer Table for a single Equation. Return Value(s)Required Inputs PRIM_RAND_TABLE_BASE PRIM_RAND_EQ_NUM PRIM_RAND_LENGTHPRIM_RAND_VALUE INPUT_DATA_NUMBER SEC_RAND_VALUE Modified RegistersPRIM_RAND_LOCATION (This Process) PRIM_RAND_ENTRY TEMP_VALUE0TEMP_POINTER0 TEMP_COUNT USER_WRITE_INPUT_NUMBER Modified RegistersIDENTIFY_MULT_INPUT returns TEMP_COUNT (Sub-Processes) Error Conditionsnone

TABLE DG PRAND_SUB_ENTRY - Process Description STATE NAME ACTIVITY NEXTSTATE PRAND_SUB_ENTRY There needs to be a process to processSTART_PROCESS handshake to start this off. Otherwise PRAND_SUB_ENTRYSTART_PROCESS The system needs to generate the pointer GET_TABLE_ENTRYinto the primary randomizer Table for the Input that is being removedPRIM_RAND_LOCATION = PRIM_RAND_TABLE_BASE+PRIM_RAND_EQ_NUM*PRIM_RAND_LENGTH+ 2*PRIM_RAND_VALUE GET_TABLE_ENTRY Getthe value from SRAM that is pointed to EVALUATE_ENTRY byPRIM_RAND_LOCATION, and store it in PRIM_RAND_ENTRY. EVALUATE_ENTRYEvaluate PRIM_RAND_ENTRY Bits[15:12] to see what the previous entryconsisted of. In the case of Overflows, the system must also look atPRIM_RAND_ENTRY[6:5] to determine how many exist. If Bits[15:14]=’00’(No Existing Entry) REMOVE_PR_ERROR If Bits[15:14]=’01’ (Existing SingleEntry) REMOVE_SINGLE If Bits[15:14]=’10’ (Existing Pair Entry)REMOVE_PAIR If Bits[15:12]=’1100’ (Existing Triple Entry)REDUCE_MULT_ENTRY If Bits[15:12]=’1101’ (Existing quadrupleREDUCE_MULT_ENTRY Entry) If Bits[15:12]=‘1110’ (Existing OverflowREDUCE_MULT_ENTRY Entry) If Bits[15:12]=‘1111’ (Single Mask Entry)REMOVE_SINGLE REMOVE_PR_ERROR Interrupt the System and indicate throughPRAND_SUB_ENTRY a status register that an attempt has been made toremove a value that did not exist.

TABLE DH Path to Remove a Single Entry REMOVE_SINGLE AnalyzePRIM_RAND_ENTRY If NEXT_MASK_STEP!=0 (Existing Masking CLEAR_SINGLEStep) If Bits[15:12]=’1111’ && Bits[4:0]=NEXT_MASK_STEP TEMP_VALUE0=0{Prepare for clear} If NEXT_MASK_STEP=0 (Existing Non- REMOVE_PR_ERRORMasking Step) If Bits[15:12]==’1111’ && Bits[4:0]!=NEXT_MASK_STEP IfNEXT_MASK_STEP=0 (Existing Non- CLEAR_SINGLE Masking Step) IfBits[15:14]=’01’ && Bits[13:0]=INPUT_DATA_NUMBER TEMP_VALUE0=0 {Preparefor clear} If NEXT_MASK_STEP=0 (Existing Non- REMOVE_PR_ERROR MaskingStep) If Bits[15:14]=’01’ && Bits[13:0]!=INPUT_DATA_NUMBER CLEAR_SINGLEWrite a TEMP_VALUE0 into the location PRAND_SUB_ENTRY pointed to byPRIME_RAND_LOCATION REMOVE_SING_ERROR Set an interrupt, and a status bitin register PRAND_SUB_ENTRY to show that there was an error in findingan input in the primary randomizer

TABLE DI Path to Remove one of the Entries of a Pair in a Multiple EntryStructure REMOVE_PAIR_ENTRY IDENTIFY_MULT_INPUT GET_REMAINING_ENTRY(MACRO CALL) This is a Macro that uses the PRIM_RAND_ENTRY and either aninput or a mask value, to identify the location in the pair table thatmatches and should be eliminated. TEMP_POINTER0 points to base of theMultiple Entry GET_REMAINING_ENTRY If TEMP_COUNT=8, There was an error,PRAND_SUB_ENTRY and neither input should be copied over. If TEMP_COUNT=0read the value at MODIFY_INPUT_VALUE TEMP_POINTER0+5 and store it inTEMP_VALUE0 If TEMP_COUNT=1 read the value at MODIFY_INPUT_VALUETEMP_POINTER0+4 and store it in TEMP_VALUE0 MODIFY_INPUT_VALUE At thispoint, TEMP_VALUE0 needs to be WR_PRIM_INPUT changed so that it can bewritten back into the PRIMARY_TABLE. If TEMP_VALUE0[15]=1 {This is amask value} Set TEMP_VALUE0[15:12]=’1111’ The remainder of the word iscorrect. If TEMP_VALUE[15]=0 {This is a non- mask value} SetTEMP_VALUE0[15:14]=’01’. The remainder of the word is correct.WR_PRIM_INPUT Write TEMP_VALUE0 back into the GET_REMAINING_SR locationthat is pointed to by PRIM_RAND_LOCATION. GET_REMAINING_SR IfTEMP_COUNT=0 read the value at WR_PRIM_SR location TEMP_POINTER0+1 andstore it in TEMP_VALUE0 If TEMP_COUNT=1, Read the value WR_PRIM_SRlocated at TEMP_POINTER0 and store it in TEMP_VALUE0 WR_PRIM_SR WriteTEMP_VALUE0 into the location CLEAR_MULT_VALID pointed to byPRIM_RAND_LOCATION+1 TEMP_VALUE0=PRIM_RAND_ENTRY[9:0] CLEAR_MULT_VALIDCLEAR_MULT_ENTRY PRAND_SUB_ENTRY (MACRO CALL) TEMP_VALUE0 must containthe number of the pair that is to be cleared.

TABLE DJ Path to Reduce a Multiple Input REDUCE_MULT_ENTRYIDENTIFY_MULT_INPUT BR_ON_MULT_LENGTH (MACRO CALL) This Macro is passeda PRIM_RAND_ENTRY, and is used to identify the position in the MultipleEntry table location where a specific Input or Mask Step is located.TEMP_COUNT Return Values: 0=First Location in Multiple Entry Table1=Second Location in Multiple Entry Table 2=Third Location in MultipleEntry Table 3=Fourth Location in Multiple Entry Table 4=First OverflowLocation in Multiple Entry Table 5=Second Overflow Location in MultipleEntry Table 6=Third Overflow Location in Multiple Entry Table 7=FourthOverflow Location in Multiple Entry Table 8=ERROR CONDITION and inputdid not match TEMP_POINTER0 Return Value: Address of the base of thespecific Multiple Entry Structure. BR_ON_MULT_LENGTH The length of theMultiple structure must be dealt with. This is really contained ininformation in the PRIM_RAND_ENTRY. One must read the information at theend of the structure, and be prepared to write it into the locationpointed to by TEMP_COUNT. Then one must be prepared to modify theprimary randomizer Entry. If PRIM_RAND_ENTRY[15:10]=’1100XX’ RD_IN3_SR{Triple} If PRIM_RAND_ENTRY[15:10]=’1101XX’ RD_IN4_SR {quadruple} IfPRIM_RAND_ENTRY[15:10]=’111001’ GEN_QUAD {1 Overflow} IfPRIM_RAND_ENTRY[15:10]=’111010’ RD_IN6 {2 Overflow} IfPRIM_RAND_ENTRY[15:10]=’111011’ RD_IN7 {3 Overflow} IfPRIM_RAND_ENTRY[15:10]=’111000’ RD_IN8 {4 Overflow} RD_IN3_SR Read theInput 3 secondary randomizer WR_IN3_SR value from the multiple structureat location TEMP_POINTER0+2 and store it in TEMP_VALUE0 WR_IN3_SR WriteTEMP_VALUE0 into the location RD_IN3_INPUT pointed to byTEMP_POINTER0+TEMP_COUNT to fill in the input that is being removed.RD_IN3_INPUT Read the Input 3 Input Value from the WR_IN3_INPUT multiplestructure at location (TEMP_POINTER0+6) and store it in TEMP_VALUE0WR_IN3_INPUT Write TEMP_VALUE0 into the location CALC_PAIR_PR pointed toby (TEMP_POINTER0+4+TEMP_COUNT) CALC_PAIR_PR Calculate the new primaryrandomizer WR_NEW_PR value for the new Pair.PRIM_RAND_ENTRY[9:0]=PRIM_RAND_(—) ENTRY[9:0]PRIM_RAND_ENTRY[15:10]=’100000’ {Pair is stored} RD_IN4_SR Read theInput 4 secondary randomizer WR_IN4_SR value from the multiple structureat location TEMP_POINTER0+3 and store it in TEMP_VALUE0 WR_IN4_SR WriteTEMP_VALUE0 into the location RD_IN4_INPUT pointed to byTEMP_POINTER0+TEMP_COUNT to fill in the input that is being removed.RD_IN4_INPUT Read the Input 4 Input Value from the WR_IN4_INPUT multiplestructure at location (TEMP_POINTER0+7) and store it in TEMP_VALUE0WR_IN4_INPUT Write TEMP_VALUE0 into the location CALC_TRIP_PR pointed toby (TEMP_POINTER0+4+TEMP_COUNT) CALC_TRIP_PR Calculate the new primaryrandomizer WR_NEW_PR value for the new Triple.PRIM_RAND_ENTRY[9:0]=PRIM_RAND_(—) ENTRY[9:0]PRIM_RAND_ENTRY[15:10]=’110000’ {Triple is stored} GEN_QUAD This is themost complex path because the WR_IN5_INPUT system must regenerate thesecondary randomizer values. The inputs are the only valid cases, so thesystem needs to bring over the 5^(th) input Read the value located inTEMP_POINTER0+0 (first overflow input), and store it in TEMP_VALUE0.WR_IN5_INPUT If TEMP_COUNT<=3, then the system GET_INPUT1 needs to writeTEMP_VALUE0 into the location pointed to by TEMP_POINTER0+4+TEMP_COUNTOtherwise, write TEMP_VALUE0 into the location pointed to byTEMP_POINTER0+TEMP_COUNT-4 GET_INPUT1 Read the value stored at locationCALC_INPUT1_SR TEMP_POINTER0+4 (Input #1), and store it in theUSER_WRITE_INPUT_NUMBER register. CALC_INPUT1_SR Call the Macro to readback the first input WR_INPUT1_SR into the input register: CallUSER_INPUT_READ_DRAM Macro WR_INPUT1_SR Write the SEC_RAND_VALUE intothe GET_INPUT2 location pointed to by TEMP_POINTER0 GET_INPUT2 Read thevalue stored at location CALC_INPUT2_SR TEMP_POINTER0+5 (Input #2), andstore it in the USER_WRITE_INPUT_NUMBER register. CALC_INPUT2_SR Callthe Macro to read back the first input WR_INPUT2_SR into the inputregister: Call USER_INPUT_READ_DRAM Macro WR_INPUT2_SR Write theSEC_RAND_VALUE into the GET_INPUT3 location pointed to byTEMP_POINTER0+1 GET_INPUT3 Read the value stored at locationCALC_INPUT3_SR TEMP_POINTER0+6 (Input #3), and store it in theUSER_WRITE_INPUT_NUMBER register. CALC_INPUT3_SR Call the Macro to readback the first input WR_INPUT3_SR into the input register: CallUSER_INPUT_READ_DRAM Macro WR_INPUT3_SR Write the SEC_RAND_VALUE intothe GET_INPUT4 location pointed to by TEMP_POINTER0+2 GET_INPUT4 Readthe value stored at location CALC_INPUT4_SR TEMP_POINTER0+7 (Input #4),and store it in the USER_WRITE_INPUT_NUMBER register. CALC_INPUT4_SRCall the Macro to read back the first input WR_INPUT4_SR into the inputregister: Call USER_INPUT_READ_DRAM Macro WR_INPUT4_SR Write theSEC_RAND_VALUE into the CALC_QUAD_PR location pointed to byTEMP_POINTER0+3 CALC_QUAD_PR Calculate the new primary randomizerWR_NEW_PR value for the new quadruple.PRIM_RAND_ENTRY[9:0]=PRIM_RAND_(—) ENTRY[9:0]PRIM_RAND_ENTRY[15:10]=’110100’ {Quad is stored} RD_IN6 In this case,there are two overflows, and WR_IN6_INPUT the system needs to read thetop value. Read the value pointed to be TEMP_POINTER0+1 (2^(nd) overflowinput) and store it in TEMP_VALUE0 WR_IN6_INPUT Based on TEMP_COUNT,there are two CALC_OVER1_PR possibilities as to where the system willwrite TEMP_VALUE0. If TEMP_COUNT<=3, write TEMP_VALUE0 into the locationpointed to by TEMP_POINTER0+TEMP_COUNT+4. If TEMP_COUNT>3, writeTEMP_VALUE0 into the location pointed to by TEMP_POINTER0+TEMP_COUNT−4CALC_OVER1_PR Calculate the new primary randomizer WR_NEW_PR value forthe new Single Overflow value. PRIM_RAND_ENTRY[9:0]=PRIM_RAND_(—)ENTRY[9:0] PRIM_RAND_ENTRY[15:10]=’111001’ {Over1 is stored} RD_IN7 Inthis case, there are three overflows, and WR_IN7_INPUT the system needsto read the top value. Read the value pointed to be TEMP_POINTER0+2(3^(rd) overflow input) and store it in TEMP_VALUE0 WR_IN7_INPUT Basedon TEMP_COUNT, there are two CALC_OVER2_PR possibilities as to where thesystem will write TEMP_VALUE0. If TEMP_COUNT<=3, write TEMP_VALUE0 intothe location pointed to by TEMP_POINTER0+4+TEMP_COUNT. If TEMP_COUNT>3,write TEMP_VALUE0 into the location pointed to byTEMP_POINTER0+TEMP_COUNT CALC_OVER2_PR Calculate the new primaryrandomizer WR_NEW_PR value for the new Double Overflow value.PRIM_RAND_ENTRY[9:0]=PRIM_RAND_(—) ENTRY[9:0]PRIM_RAND_ENTRY[15:10]=’111010’ {Over2 is stored} RD_IN8 In this case,there are four overflows, and WR_IN8_INPUT the system needs to read thetop value. Read the value pointed to be TEMP_POINTER0+3 (4^(th) overflowinput) and store it in TEMP_VALUE0 WR_IN8_INPUT Based on TEMP_COUNT,there are two CALC_OVER3_PR possibilities as to where the system willwrite TEMP_VALUE0. If TEMP_COUNT<=3, write TEMP_VALUE0 into the locationpointed to by TEMP_POINTER0+4+TEMP_COUNT. If TEMP_COUNT>3, writeTEMP_VALUE0 into the location pointed to by TEMP_POINTER0+TEMP_COUNTCALC_OVER3_PR Calculate the new primary randomizer WR_NEW_PR value forthe new Double Overflow value. PRIM_RAND_ENTRY[9:0]=PRIM_RAND_(—)ENTRY[9:0] PRIM_RAND_ENTRY[15:10]=’111011’ {Over3 is stored} WR_NEW_PRWrite the PRIM_RAND_ENTRY value into PRAND_SUB_ENTRY the locationpointed to by PRIM_RAND_LOCATION.

TABLE DK CLEAR_MULT_ENTRY - Process Description Process NameCLEAR_MULT_ENTRY Process Function This process is used to remove anentry from the Multiple Entry Table. Return Value(s) Required InputsTEMP_VALUE0[9:0] must contain the index for the Multiple Entry Table.PRIM_RAND_TABLE_BASE PRIM_RAND_EQ_NUM PRIM_RAND_LENGTH PAIR_VALID_OFFSETModified Registers TEMP_POINTER0 (This Process) TEMP_ENCODE0 TEMP_VALUE1Modified Registers (Sub-Processes) Error Conditions none

TABLE DL CLEAR_MULT_ENTRY Process Implementation CLEAR_MULT_ENTRYTEMP_VALUE0[9:0] contains the number of CALC_MULT_SUB_(—) the MultipleEntry location. MOD TEMP_VALUE0[9:8] contains the number of the SuperBlock, TEMP_VALUE[7:4] contains the number of the sub-block, andTEMP_VALUE0[3:0] contains the location within the sub-block that needsto be decoded. TEMP_VALUE0[3:0] will be run through a 4:16 decoder, andthe result will be stored in TEMP_ENCODE0. TEMP_ENCODE0 now contains a 1in the location of the block that is being cleared out. Calculate thepointer to the multiple sub- block entry. TEMP_POINTER0=PRIM_RAND_TABLE_BASE+ PRIM_RAND_EQ_NUM*PRIM_RAND_LENGTH+MULT_VALID_OFFSET+TEMP_VALUE0[9:4] CALC_MULT_SUB_MOD Read the valuepointed to by WRITE_MULT_SUB_(—) TEMP_POINTER0, AND it with the inverseMOD of TEMP_ENCODE0, and store it in TEMP_VALUE1. WRITE_MULT_SUB_MODWrite the value in TEMP_VALUE1 into the GET_MULT_SUPER_(—) locationpointed to by TEMP_POINTER0. PTR GET_MULT_SUPER_PTR At this point, thesystem needs to get the GET_MULT_SUPER pointer location for the PairSuper block that is being cleared out. TEMP_POINTER0=PRIM_RAND_TABLE_BASE+ PRIM_RAND_EQ_NUM*PRIM_RAND_LENGTH+PAIR_VALID_OFFSET+64+ TEMP_VALUE0[9:8] The system needs to calculate thebit in the Super Block that needs to be cleared simultaneously.TEMP_VALUE0[7:4] contains the encoded value. TEMP_VALUE0[7:4] needs tobe run through a 4:16 decoder, and the resulting value needs to bestored in TEMP_ENCODE0. GET_MULT_SUPER Read the value pointed to byMOD_MULT_SUPER TEMP_POINTER0, and AND it with the inverse ofTEMP_ENCODE0, and store it in TEMP_VALUE1. MOD_MULT_SUPER Write thevalue in TEMP_VALUE1 into the END_MACRO location pointed to byTEMP_POINTER0.

TABLE DM IDENTIFY_MULT_INPUT - Process Description Process NameIDENTIFY_MULT_INPUT Process Function This Macro is passed aPRIM_RAND_ENTRY, and is used to identify the position in the MultipleEntry table location where a specific Input or Mask Step is located.Return Value(s) The Location in the Pair Table where the specific Inputor Mask Step is located is returned in TEMP_COUNT. TEMP_COUNT ReturnValues: 0=First Location in Multiple Entry Table 1=Second Location inMultiple Entry Table 2=Third Location in Multiple Entry Table 3=FourthLocation in Multiple Entry Table 4=First Overflow Location in MultipleEntry Table 5=Second Overflow Location in Multiple Entry Table 6=ThirdOverflow Location in Multiple Entry Table 7=Fourth Overflow Location inMultiple Entry Table 8=ERROR CONDITION and input did not matchTEMP_POINTER0 Return Value: Address of the base of the specific MultipleEntry Structure. Required Inputs PRIM_RAND_ENTRY - This register mustcontain the value from the table that has the Multiple Entry Pointer.MASKING_ON/OFF - This bit status is required. INPUT_DATA_NUMBER - Thisregister contains the value of the Input being compared and is requiredif MASKING_ON/OFF=0. NEXT_MASK_STEP - This register contains the nextmasking step that is to be taken, and is required if MASKING_ON/OFF=1.PRIM_RAND_TABLE_BASE PRIM_RAND_EQ_NUM PRIM_RAND_LENGTH PAIR_TABLE_OFFSETare all values that are required to access the Pair location. ModifiedRegisters TEMP_COUNT {Return Value} TEMP_POINTER0 {Return Value}TEMP_VALUE0 Error Conditions TEMP_COUNT=0, and Interrupt is Generated.

TABLE DN IDENTIFY_MULT_INPUT - Process ImplementationIDENTIFY_MULT_INPUT The PRIM_RAND_ENTRY contains the GET_NEXT_MULT_INPUTvalue that has been read from the primary Randomization Table.TEMP_COUNT=0 {This is the return value for the matching input in thetriple structure} PRIM_RAND_ENTRY Bits[9:0] contain the number of theMultiple Entry structure that is being used. Calculate the location forthe first multiple entry block location. TEMP_POINTER0=PRIM_RAND_TABLE_BASE+ PRIM_RAND_EQ_NUM*PRIM_RAND_LENGTH+MULT_TABLE_OFFSET+ PRIM_RAND_ENTRY[9:0]*8 GET_NEXT_MULT_INPUT IfPRIM_RAND_ENTRY[15:14]==’10’ {Pair} MULT_CHECK_ERROR && TEMP_COUNT>1Else if MULT_CHECK_ERROR PRIM_RAND_ENTRY[15:12]==’1100’ {Triple} &&TEMP_COUNT>2 Else if MULT_CHECK_ERROR PRIM_RAND_ENTRY[15:12]==’1101’{Quad} && TEMP_COUNT>3 Else If MULT_CHECK_ERRORPRIM_RAND_ENTRY[15:10]==’111001’ {Single Overflow} && TEMP_COUNT>4 Elseif MULT_CHECK_ERROR PRIM_RAND_ENTRY[15:10]=’111010’ {Double Overflow} &&TEMP_COUNT>5 Else if MULT_CHECK_ERROR PRIM_RAND_ENTRY[15:10]=’111011’{Triple Overflow} && TEMP_COUNT>6 Else If MULT_CHECK_ERRORPRIM_RAND_ENTRY[15:10]=’111000’ {quadruple Overflow} && TEMP_COUNT>7 IfTEMP_COUNT<4, Get the data stored at CHECK_NEXT_MULT_INPUT locationTEMP_POINTER0+TEMP_COUNT+4 and put it into TEMP_VALUE0 Else, Get thedata stored at location TEMP_POINTER0+TEMP_COUNT-4 and put it intoTEMP_VALUE0 CHECK_NEXT_MULT_INPUT If NEXT_MASK_STEP!=0 && IDLETEMP_VALUE0[15]==1 && TEMP_VALUE0[4:0]==NEXT_MASK_STEP IfNEXT_MASK_STEP!=0 && GET_NEXT_MULT_INPUT (TEMP_VALUE0[15]!=1 ∥TEMP_VALUE0[4:0]!=NEXT_MASK_STEP) TEMP_COUNT=TEMP_COUNT+1 IfNEXT_MASK_STEP==0 && IDLE TEMP_VALUE0[15]==0 &&TEMP_VALUE0[13:0]=PRIM_RAND_INPUT If NEXT_MASK_STEP==0 &&GET_NEXT_MULT_INPUT (TEMP_VALUE0[15]!=0 ∥TEMP_VALUE0[13:0]!=PRIM_RAND_INPUT) TEMP_COUNT=TEMP_COUNT+1MULT_CHECK_ERROR Set an interrupt that an input is being IDLE checked,and it is not stored in the corresponding pair. The status registershould identify this situation. TEMP_COUNT=8 to show error.

TABLE DO RECEIVE_PROCESS_CYCLE - Process Description Process NameRECEIVE_PROCESS_CYCLE Process Function This process performs a sequenceof cycles of analysis on a received Primary and Secondary Randomizervalue to determine the associated Input. This process relies on TimeAccelerated Randomizer values and Mask Capture Data all being capturedprior to it's start. The PROG_MASK_PRIM_RAND value is a latched value ofPROG_MASK_RX at any given step in the cycle, and is used in determiningwhether there is a matching entry in the appropriate equation table. ThePROG_MASK_SEC_RAND value is a latched value of PROG_MASK_RX at any givenstep in the cycle, and is used to verify the input, and to differentiatebetween multiple inputs. If Masking Steps are used, theSELECTIVE_MASK_SELECT register is updated, and the core cycle isrepeated. Return Value(s) INPUT MATCH Required InputsPROG_MASK_PRIM_RAND {Output from the Programmable Mask State Machine ata given step in the analysis process} PROG_MASK_SEC_RAND {Output fromthe Programmable Mask State Machine at a given step in the analysisprocess} SELECTIVE_MASK_SELECT {Starts at 0 for first analysis step}PRIM_RAND_ENTRY - This register must contain the modified PrimaryRandomizer Value. PRIM_RAND_TABLE_BASE PRIM_RAND_EQ_NUM PRIM_RAND_LENGTHMULT_TABLE_OFFSET are all values that are required to access theMultiple Table. Modified Registers TEMP_COUNT {Return Value}TEMP_POINTER0 {Return Value} TEMP_VALUE0 Error Conditions NO_INPUT_MATCHis found.

TABLE DP RECEIVE_PROCESS_CYCLE - Process ImplementationRECEIVE_PROCESS_CYCLE {Generate the address of the appropriateREAD_FIRST_LOCATION table entry that is being pointed to by theProgrammably Masked Primary Randomizer value.} PRIM_RAND_LOCATION=PRIM_RAND_TABLE_BASE+ PRIM_RAND_EQ_NUM*PRIM_RAND_LENGTH+2*PROG_MASK_PRIM_RAND READ_FIRST_LOCATION The SRAM value at addressEVALUATE_TYPE PRIM_RAND_LOCATION will be loaded into PRIM_RAND_ENTRYEVALUATE_TYPE Evaluate B15, B14, B13, B12 of the PRIM_RAND_ENTRY to seewhat the Entry consists of. If B15=0, B14=0 (No Existing Entry)ERROR_NO_MATCH If B15=0, B14=1 (Existing Single Entry) READ_SINGLE_SRINPUT_MATCH=PRIM_RAND_ENTRY[13:0] PRIM_RAND_LOCATION++ {To prepare toretrieve the Secondary Randomizer value} If B15=1, B14=0 (Existing PairEntry) GET_MULT_PAIR PRIM_RAND_LOCATION= PRIM_RAND_TABLE_BASE+PRIM_RAND_EQ_NUM*PRIM_RAND_LENGTH+MULT_TABLE_OFFSET+PRIM_RAND_ENTRY[9:0]*8 If B15=1, B14=1, B13=0, B12=0(Existing GET_MULT_TRIPLE Triple Entry) PRIM_RAND_LOCATION=PRIM_RAND_TABLE_BASE+ PRIM_RAND_EQ_NUM*PRIM_RAND_LENGTH+MULT_TABLE_OFFSET+PRIM_RAND_ENTRY[9:0]*8 If B15=1, B14=1, B13=0, B12=1(Existing GET_MULT_QUAD Quad Entry) PRIM_RAND_LOCATION=PRIM_RAND_TABLE_BASE+ PRIM_RAND_EQ_NUM*PRIM_RAND_LENGTH+MULT_TABLE_OFFSET+PRIM_RAND_ENTRY[9:0]*8 If B15=1, B14=1, B13=1, B12=0(Existing ERROR_NO_MATCH Overflow Entry) {Since the actualPRIM_RAND_LOCATION= input being PRIM_RAND_TABLE_BASE+ matched can notPRIM_RAND_EQ_NUM*PRIM_RAND_LENGTH+ be identified}MULT_TABLE_OFFSET+PRIM_RAND_ENTRY[9:0]*8 If B15=1, B14=1, B13=1, B12=1(Single READ_MASK_SR Mask Entry) SELECTIVE_MASK_STEP=PRIM_RAND_(—)ENTRY[4:0] {Prepare to check the Secondary Randomizer value}PRIM_RAND_LOCATION++

TABLE DQ Path to Evaluate a Single Entry READ_SINGLE_SR The SRAM valueat address EVALUATE_SR {Longer SRAM Access} PRIM_RAND_LOCATION will beloaded into PRIM_RAND_ENTRY EVALUATE_SR If {PRIM_RAND_ENTRY==INPUT_MATCH PROG_MASK_SEC_RAND} Else ERROR_NO_MATCH INPUT_MATCH=0 {Thereis not a match}

TABLE DR Path to Evaluate a Single Mask Entry READ_MASK_SR The SRAMvalue at address EVALUATE_MASK_SR PRIM_RAND_LOCATION will be loaded intoPRIM_RAND_ENTRY EVALUATE_MASK_SR If {PRIM_RAND_ENTRY== MASK_MATCHPROG_MASK_SEC_RAND} Else ERROR_NO_MATCH SELECTIVE_MASK_STEP=0

TABLE DS Path to Evaluate a Paired Entry GET_MULT_PAIR The SRAM value ataddress EVALUATE_PAIR_VAL1SR PRIM_RAND_LOCATION will be loaded intoPRIM_RAND_ENTRY EVALUATE_PAIR_VAL1 If MATCH_PAIR_SR{PRIM_RAND_ENTRY==PROG_MASK_(—) SEC_RAND} PRIM_RAND_LOCATION+=4 {To readthe value} Else GET_PAIR_VAL2SR PRIM_RAND_LOCATION++ GET_PAIR_VAL2_SRThe SRAM value at address EVALUATE_PAIR_VAL2SR PRIM_RAND_LOCATION willbe loaded into PRIM_RAND_ENTRY EVALUATE_PAIR_VAL2SR If MATCH_PAIR_SR{PRIM_RAND_ENTRY==PROG_MASK_(—) SEC_RAND} PRIM_RAND_LOCATION+=4 {To readthe value} Else ERROR_NO_MATCH MATCH_PAIR_SR The SRAM value at addressPAIR_VAL_OR_MASK PRIM_RAND_LOCATION will be loaded into PRIM_RAND_ENTRYPAIR_VAL_OR_MASK If {PRIM_RAND_ENTRY[15]==0 INPUT_MATCHINPUT_MATCH=PRIM_RAND_(—) ENTRY[13:0] Else MASK_MATCHSELECTIVE_MASK_STEP=PRIM_RAND_(—) ENTRY[4:0]

TABLE DT Path to Evaluate a Tripled Entry GET_MULT_TRIPLE The SRAM valueat address EVALUATE_TRIP_VAL1SR PRIM_RAND_LOCATION will be loaded intoPRIM_RAND_ENTRY EVALUATE_TRIP_VAL1SR If MATCH_TRIP_SR{PRIM_RAND_ENTRY==PROG_MASK_SEC_(—) RAND} PRIM_RAND_LOCATION+=4 {To readthe value} Else GET_TRIP_VAL2SR PRIM_RAND_LOCATION++ GET_TRIP_VAL2SR TheSRAM value at address EVALUATE_TRIP_VAL2SR PRIM_RAND_LOCATION will beloaded into PRIM_RAND_ENTRY EVALUATE_TRIP_VAL2SR If MATCH_TRIP_SR{PRIM_RAND_ENTRY==PROG_MASK_SEC_(—) RAND} PRIM_RAND_LOCATION+=4 {To readthe value} Else GET_TRIP_VAL3SR PRIM_RAND_LOCATION++ GET_TRIP_VAL3SR TheSRAM value at address EVALUATE_TRIP_VAL3SR PRIM_RAND_LOCATION will beloaded into PRIM_RAND_ENTRY EVALUATE_TRIP_VAL3SR If MATCH_TRIP_SR{PRIM_RAND_ENTRY==PROG_MASK_SEC_(—) RAND} PRIM_RAND_LOCATION+=4 {To readthe value} Else ERROR_NO_MATCH MATCH_TRIP_SR The SRAM value at theaddress TRIP_VAL_OR_MASK PRIM_RAND_LOCATION will be loaded intoPRIM_RAND_ENTRY TRIP_VAL_OR_MASK If {PRIM_RAND_ENTRY[15]==0 INPUT_MATCHINPUT_MATCH=PRIM_RAND_ENTRY[13:0] Else MASK_MATCHSELECTIVE_MASK_STEP=PRIM_RAND_(—) ENTRY[4:0]

TABLE DU Path to Evaluate a Quadrupled Entry GET_MULT_QUAD The SRAMvalue at address EVALUATE_QUAD_VAL1SR PRIM_RAND_LOCATION will be loadedinto PRIM_RAND_ENTRY EVALUATE_QUAD_VAL1SR If MATCH_QUAD_SR{PRIM_RAND_ENTRY==PROG_MASK_SEC_(—) RAND} PRIM_RAND_LOCATION+=4 {To readthe value} Else GET_QUAD_VAL2SR PRIM_RAND_LOCATION++ GET_QUAD_VAL2SR TheSRAM value at address EVALUATE_QUAD_VAL2SR PRIM_RAND_LOCATION will beloaded into PRIM_RAND_ENTRY EVALUATE_QUAD_VAL2SR If MATCH_QUAD_SR{PRIM_RAND_ENTRY==PROG_MASK_SEC_(—) RAND} PRIM_RAND_LOCATION+=4 {To readthe value} Else GET_QUAD_VAL3SR PRIM_RAND_LOCATION++ GET_QUAD_VAL3SR TheSRAM value at address EVALUATE_QUAD_VAL3SR PRIM_RAND_LOCATION will beloaded into PRIM_RAND_ENTRY EVALUATE_QUAD_VAL3SR If MATCH_QUAD_SR{PRIM_RAND_ENTRY==PROG_MASK_SEC_(—) RAND} PRIM_RAND_LOCATION+=4 {To readthe value} Else GET_QUAD_VAL4SR PRIM_RAND_LOCATION++ GET_QUAD_VAL4SR TheSRAM value at address EVALUATE_QUAD_VAL4SR PRIM_RAND_LOCATION will beloaded into PRIM_RAND_ENTRY EVALUATE_QUAD_VAL4SR If MATCH_QUAD_SR{PRIM_RAND_ENTRY==PROG_MASK_SEC_(—) RAND} PRIM_RAND_LOCATION+=4 {To readthe value} Else ERROR_NO_MATCH MATCH_QUAD_SR The SRAM value at theaddress QUAD_VAL_OR_MASK PRIM_RAND_LOCATION will be loaded intoPRIM_RAND_ENTRY QUAD_VAL_OR_MASK If {PRIM_RAND_ENTRY[15]==0 INPUT_MATCHINPUT_MATCH=PRIM_RAND_ENTRY[13:0] Else MASK_MATCHSELECTIVE_MASK_STEP=PRIM_RAND_ENTRY [4:0]

TABLE DV Final Processing steps for all Primary Randomizer SituationsMASK_MATCH Set RANDOMIZER_SELECT=0 for the LATCH_NEW_PR Masking StateMachine to generate a new Programmably Masked Primary Randomizer value.LATCH_NEW_PR Latch new PROG_MASK_PRIM_RAND LATCH_NEW_SR value SetRANDOMIZER_SELECT=1 for the Masking State Machine to generate a newProgrammably Masked Secondary Randomizer value. LATCH_NEW_SR Latch newPROG_MASK_SEC_RAND RECEIVE_PROCESS_(—) value CYCLE INPUT_MATCH Interruptthe host that an input match has END_PROCESS occurred. ERROR_NO_MATCHInterrupt the host that an error condition END_PROCESS has occurred, andthat no input match has been found.State Machines for the “Mapper Engine, Statistics and Equation StateMachine” Block

The following state machines are used to manage the mapper engine,statistic, and equation selection and calculation functions of thesystem (see Tables DW–EI below).

TABLE DW INITIALIZE_ONE_EQ - Process Description Process NameINITIALIZE_ONE_EQ Process Function This process is used to Initialize asingle equation and all of it's associated statistics registers. ReturnValue(s) Required Inputs RAND_INIT_EQ {Contains the equation to beupdated} Modified Registers EQn_TRIPS (This Process) EQn_QUADS EQn_MULTSEQn_OVERFLOW Modified Registers RAND_INIT (Sub-Processes) ErrorConditions none

TABLE DX INITIALIZE_ONE_EQ - Process Implementation STATE NAME ACTIVITYNEXT STATE INITIALIZE_ONE_EQ If the Main Control Directs this process toINITIALIZE start. RAND_INIT_EQ contains the equation to be updated. ElseINITIALIZE_ONE_EQ INITIALIZE Call the Macro to clear out the randomizerRAND_INIT Tables. RAND_INIT Macro Call to clear out randomizers.CLEAR_COUNTERS CLEAR_COUNTERS Case RAND_INIT_EQ Case 0 IDLE EQ0_TRIPS=0EQ0_QUADS=0 EQ0_MULTS=0 EQ0_OVERFLOW=0 Case 1 IDLE EQ1_TRIPS=0EQ1_QUADS=0 EQ1_MULTS=0 EQ1_OVERFLOW=0 Case 2 IDLE EQ2_TRIPS=0EQ2_QUADS=0 EQ2_MULTS=0 EQ2_OVERFLOW=0 Case 3 IDLE EQ3_TRIPS=0EQ3_QUADS=0 EQ3_MULTS=0 EQ3_OVERFLOW=0 Case 4 IDLE EQ4_TRIPS=0EQ4_QUADS=0 EQ4_MULTS=0 EQ4_OVERFLOW=0 Case 5 IDLE EQ5_TRIPS=0EQ5_QUADS=0 EQ5_MULTS=0 EQ5_OVERFLOW=0 Case 6 IDLE EQ6_TRIPS=0EQ6_QUADS=0 EQ6_MULTS=0 EQ6_OVERFLOW=0 Case 7 IDLE EQ7_TRIPS=0EQ7_QUADS=0 EQ7_MULTS=0 EQ7_OVERFLOW=0

TABLE DY INITIALIZE_ALL_EQS - Process Description Process NameINITIALIZE_ALL_EQS Process Function This process is used to Initializeall equations and all of their associated statistics registers. ReturnValue(s) Required Inputs Modified Registers RAND_INIT_EQ (This Process)EQn_TRIPS EQn_QUADS EQn_MULTS EQn_OVERFLOW Modified RegistersINITIALIZE_ONE_EQ (Sub-Processes) Error Conditions none

TABLE DZ INITIALIZE_ALL_EQS - Process Description STATE NAME ACTIVITYNEXT STATE INITIALIZE_ALL_EQS If the Main Control Directs this processto INITIALIZE start. Else INITIALIZE_ALL_EQS INITIALIZE RAND_INIT_EQ=0.INIT_TABLE Call the Macro to clear out the randomizer Tables. INIT_TABLEMacro Call to clear out randomizer and INITIALIZE_ONE_EQ Multiple TablesINITIALIZE_ONE_EQ Macro Call to clear out randomizer and SET_MAPPINGSCounters SET_MAPPINGS EQ[RAND_INIT_EQ]_PRIM_MAP=RAND_INIT_(—)CHECK_TO_CONTINUE EQ {Sets the initial primary mapping to a value from 0to 7 EQ[RAND_INIT_EQ]_SEC_EQ_NUM=RAND_(—) INIT_EQ+1 {With analyzing only3 bits so that a value of 7 will have one added to it and become 0}RAND_INIT_EQ++ CHECK_TO_CONTINUE If RAND_INIT_EQ==0 {3 bit value,signifies IDLE wrapover} Else INIT_TABLE

TABLE EA ADD_INPUT_ALL_EQ - Process Description Process NameADD_INPUT_ALL_EQ Process Function This process is used to add an inputto all equations. Return Value(s) Required Inputs Modified RegistersEQ_POINTER (This Process) EQUATION_MAP_SELECT PRIM_RAND_EQ_NUMPRIM_RAND_VALUE SEC_RAND_VALUE Modified Registers PRAND_ADD_ENTRY(Sub-Processes) Error Conditions none

TABLE EB ADD_INPUT_ALL_EQ - Process Description STATE NAME ACTIVITY NEXTSTATE ADD_INPUT_ALL_EQ If the Main Control Directs this process tostart. INITIALIZE {Done anytime an input is added to the system} ElseADD_INPUT_ALL_EQ INITIALIZE Set EQ_POINTER=0 to start with the firstMAP_NEXT_EQ equation. MAP_NEXT_EQ Set EQUATION_MAP_SELECT toSTORE_PRIM_RAND EQ[EQ_POINTER]_PRIM_MAP. Now the primary map value isdriving the Mapper. PRIM_RAND_EQ_NUM=EQ_POINTER {To setup so that thevalue can be stored in the proper place.} STORE_PRIM_RAND LatchCALC_RANDOMIZER_VALUE into the STORE_SEC_RAND PRIM_RAND_VALUE register.Set EQUATION_MAP_SELECT to EQ[EQ_POINTER]_SEC_MAP. Now the secondary mapvalue is driving the Mapper STORE_SEC_RAND Latch CALC_RANDOMIZER_VALUEinto the PRAND_ADD_ENTRY SEC_RAND_VALUE register. PRAND_ADD_ENTRY Callthe macro to add an entry to the table. INC_EQUATION_PTRINC_EQUATION_PTR If EQ_POINTER==7 IDLE Else EQ_POINTER++ MAP_NEXT_EQ

TABLE EC SUB_INPUT_ALL_EQ - Process Description Process NameSUB_INPUT_ALL_EQ Process Function This process is used to subtract aninput from all equations. Return Value(s) Required Inputs ModifiedRegisters EQ_POINTER (This Process) EQUATION_MAP_SELECT PRIM_RAND_EQ_NUMPRIM_RAND_VALUE SEC_RAND_VALUE Modified Registers PRAND_SUB_ENTRY(Sub-Processes) Error Conditions none

TABLE ED SUB_INPUT_ALL_EQ - Process Description STATE NAME ACTIVITY NEXTSTATE SUB_INPUT_ALL_EQ If the Main Control Directs this process toINITIALIZE start. {Done anytime an input is removed from the system}Else SUB_INPUT_ALL_EQ INITIALIZE Set EQ_POINTER=0 to start with thefirst SUB_NEXT_EQ equation. SUB_NEXT_EQ Set EQUATION_MAP_SELECT toSTORE_PRIM_RAND EQ[EQ_POINTER]_PRIM_MAP. Now the primary map value isdriving the Mapper. PRIM_RAND_EQ_NUM=EQ_POINTER {To setup so that thevalue can be stored in the proper place.} STORE_PRIM_RAND LatchCALC_RANDOMIZER_VALUE into the STORE_SEC_RAND PRIM_RAND_VALUE register.Set EQUATION_MAP_SELECT to EQ[EQ_POINTER]_SEC_MAP. Now the secondary mapvalue is driving the Mapper STORE_SEC_RAND Latch CALC_RANDOMIZER_VALUEinto the PRAND_SUB_ENTRY SEC_RAND_VALUE register. PRAND_SUB_ENTRY Callthe macro to subtract an entry from the INC_EQUATION_PTR table.INC_EQUATION_PTR If EQ_POINTER==7 IDLE Else EQ_POINTER++ SUB_NEXT_EQ

TABLE EE UPDATE_DISABLED_EQS - Process Description Process NameUPDATE_DISABLED_EQS Process Function This process is used to bring allinputs back into the Input Register and map them through all of thedisabled equations. Return Value(s) Required Inputs Modified RegistersEQ_POINTER (This Process) EQn_INCOMPLETE bits. RAND_INIT_EQ ModifiedRegisters (Sub-Processes) Error Conditions none

TABLE EF UPDATE_DISABLED_EQS - Process Description STATE NAME ACTIVITYNEXT STATE UPDATE_(—) If the Main Control Directs INITIALIZEDISABLED_(—) this process to start. EQS {Done when the equationthreshold is met for having a predetermined number of un-usableequations. This value is stored in the EQ_UPDATE_THRESH register} ElseUPDATE_(—) DISABLED_(—) EQS

TABLE EG Section to Clear out Invalid Equations and Setup New MappingsINITIALIZE Set EQ_POINTER=0 to start with the first SET_INCOMPLETEequation. SET_INCOMPLETE If (EQ[EQ_POINTER]_DISABLE=1 {Disable} &&EQ[EQ_POINTER]_AGING==255) {equation is aged out} then setEQ[EQ_POINTER]_INCOMPLETE=1 {Signifies that the equation is incomplete.}If EQ_POINTER=7 CLEAR_EQUATIONS Else EQ_POINTER++ SET_INCOMPLETECLEAR_EQUATIONS Set RAND_INIT_EQ=0 to start with the firstCHECK_FOR_CLEAR equation. CHECK_FOR_CLEAR IfEQ[RAND_INIT_EQ]_INCOMPLETE=1 INIT_EQUATION {Incomplete} Else IfRAND_INIT_EQ=7 RE_CALCULATE Else RAND_INIT_EQ++ CHECK_FOR_CLEARINIT_EQUATION INITIALIZE_ONE_EQ {Process to clear out CHANGE_MAPPING andinitialize the selected equation.} CHANGE_MAPPINGEQ[EQ_POINTER]_PRIM_MAP+=8 CHECK_COUNT {Changes the mapping for theprimary equation to the present value +8} EQ[EQ_POINTER]_SEC_MAP=EQ[OPTIMAL_EQUATION]_PRIM_MAP {This uses the best remaining optimalmapping as the secondary randomizer value} CHECK_COUNT IfRAND_INIT_EQ==7 RE_CALCULATE Else RAND_INIT_EQ++ CHECK_FOR_CLEAR

TABLE EH Section to recalculate the equations that will be updatedRE_CALCULATE {The inputs need to be brought back into SET_INPUT_NUMBERthe system to calculate their values for the appropriate equations} SetEQ_INPUT_COUNT=0 {To start cycling through inputs at the first possible}SET_INPUT_NUMBER SYS_INPUT_DATA_NUMBER=EQ_INPUT_(—) CHECK_INPUT_VALIDCOUNT IF EQ_INPUT_COUNT>10000 INPUTS_DONE CHECK_INPUT_VALIDSYS_CHECK_VALID BRANCH_VALID {This routine returns a “1” in theINPUT_STRUCT_VALUE register if the input is valid.} BRANCH_VALID IfINPUT_STRUCT_VALUE==1 GET_INPUT Else (INPUT_STRUCT_VALUE==0)SET_INPUT_NUMBER EQ_INPUT_COUNT++ GET_INPUT SYS_INPUT_LOADCHECK_EQ_UPDATE {This routine is used to load the input into the InputRegister} EQ_POINTER=0 {Prepare to start cycling through to find theequations that have been disabled.} CHECK_EQ_UPDATE IfEQ[EQ_POINTER]_INCOMPLETE==1, MAP_PRIMARY then the system needs toupdate the equation. PRIM_RAND_EQ_NUM=EQ_POINTER {For Storage} {Setupthe mapper to the primary Map EQUATION_MAP_SELECT=EQ[EQ_POINTER]_PRIM_MAP++ Else, the system needs to increment andINC_AND_CHECK check. MAP_PRIMARY PRIM_RAND_VALUE=CALC_RANDOMIZER_(—)MAP_SECONDARY VALUE {Setup the mapper to the secondary MapEQUATION_MAP_SELECT= EQ[EQ_POINTER]_PRIM_SEC++ MAP_SECONDARYSEC_RAND_VALUE=CALC_RANDOMIZER_(—) UPDATE_TABLE VALUE UPDATE_TABLEPRAND_ADD_ENTRY NEXT_EQUATION {This routine loads the new entry}NEXT_EQUATION IF (EQ_POINTER==7) SET_INPUT_NUMBER {The system has gonethrough all the equations} EQ_INPUT_COUNT++ {The system needs to go tothe next input.} Else EQ_POINTER++ CHECK_EQ_UPDATE {Prepare for the nextequation}

TABLE EI This Section Handles the Final Cleanup and Enabling of theEquations INPUTS_DONE Set EQ_POINTER=0 RE_ENABLE_(—) to start Looping EQRE_ENABLE_EQ If CHECK_LAST_(—) EQ[EQ_POINTER]_(—) EQ INCOMPLETE==1,EQ[EQ_POINTER]_(—) INCOMPLETE=0 {This re-enables the equation}CHECK_LAST_EQ IF EQ_POINTER==7 IDLE Else EQ_POINTER++ RE_ENABLE_(—) EQProcess Summary

The following table lists a summary of the key processes describedabove.

TABLE EJ Process Summary Additional Process Start Process Name CallingProcesses Conditions Description INPUT_VALID_INIT Power On / ResetInitializes the Input Valid Table. USER_CHECK_VALID User InitiatedChecks to see whether an input location contains a valid entry.SYS_CHECK_VALID UPDATE_DISABLED_EQS System routine to see whether aninput location contains a valid entry. SYS_GET_AVAIL_INPUT SystemInitiated Determines the based on whether next open location AutoStorage in the input Location is Full. structure. USER_INPUT_WR_LOADUser Initiated Writes a new input into the system, loads it into theInput Register, and reflects it in the Randomizer Tables.USER_INPUT_WRITE User Initiated Writes a new input into the system butdoes not load it into the Input Register and reflect it in theRandomizer Tables USER_INPUT_READ User Inititated Reads an input fromDRAM but does not load it into the Input Register. USER_INPUT_CLEAR UserInititated Reads and clears an input from DRAM, loads it into the InputRegister, and clears it from the Randomizer Tables. SYS_INPUT_LOADPRAND_SUB_ENTRY Retrieves an input UPDATE_DISABLED_EQS from DRAM andloads it into the Input Register. INIT_FORCED_MASK Mask Register Sets upall bits that Setup Completed will be masked off from use in RandomizerCalculations. INIT_PROG_MASK Mask Register Sets up all of the SetupCompleted Programmable Mask bits and their Impact Registers. RAND_INITINITIALIZE_ONE_EQ Clears out the Randomizer Table for a specificequation entry. PRAND_ADD_ENTRY ADD_INPUT_ALL_EQS Adds a RandomizerUPDATE_DISABLED_EQS Table Entry for one specific equation.GET_NEW_MULT_ENTRY PRAND_ADD_ENTRY Identifies the next Multiple TableEntry for a Specific Equation. PRAND_SUB_ENTRY SUB_INPUT_ALL_EQ Removesan entry from a Randomizer Table for a single equation. CLEAR_MULT_ENTRYPRAND_SUB_ENTRY Clears out and frees up a multiple entry for a specificequation. IDENTIFY_MULT_INPUT PRAND_SUB_ENTRY Identifies the locationwhere a multiple input resides. RECEIVE_PROCESS_CYCLE Packet Received.Uses Received Randomizer Randomizer Values values Time to determine anAccelerated and input number Masked. match. INITIALIZE_ONE_EQINITIALIZE_ALL_EQS Clears out and UPDATE_DISABLED_EQS initializes all{Minor Arbitration} Randomizer Table entries for a single equation.INITIALIZE_ALL_EQS Power On/Reset Clears out and initializes allRandomizer Table entries for all equations. ADD_INPUT_ALL_EQSUSER_INPUT_WR_LOAD Adds an input to all of the Randomizer Tables.SUB_INPUT_ALL_EQS USER_INPUT_CLEAR Subtracts an input from all of theRandomizer Tables. UPDATE_DISABLED_EQS Threshold Brings all inputsReached for into the Input requiring equation Register and update.remaps all disabled equations to new equations.Captured Packet Classification Description (Interface)

In FIG. 18, one path 196 involves latching the output data into variousnovel custom ASIC registers.

-   -   The primary randomizer is latched into the FLAME_PRIM_RAND        register.    -   The secondary randomizer is latched into the FLAME_SEC_RAND        register.    -   The primary randomizer feedback value from the data framer ASIC        is latched into the FLAME_PRIM_FB register.    -   The secondary randomizer feedback value from the data framer        ASIC is latched into the FLAME_SEC_FB register.    -   Zero to four masking registers from the data framer ASIC are        latched into the applicable FLAME_MASK_n registers.

A set of paths 190 are initiated when the master control block clearsthe system to start processing the received values. In the case of asingle data framer ASIC, this is immediately.

-   -   The path 190 to “2” shows the transfer of the FLAME _MASK_n        registers into the MASK_CAPTURE_DATA_n registers. These        transfers can be done entirely in parallel in a single cycle.    -   The path 190 to “3” shows the time acceleration of the received        randomizer values. The FLAME_PRIM_RAND value is time accelerated        in a single cycle to generate the PRIM_RANDOMIZER_RX value. The        FLAME_SEC_RAND value is time accelerated in a single cycle to        generate the SEC_RANDOMIZER_RX.

Another set of paths 192 are initiated when the randomizer values needto be modified by masking prior to their use in accessing and verifyingentries in the appropriate primary randomizer table.

The path 192 from “2” to “3” shows how the MASK_CAPTURE_DATA, inconjunction with the mask register impact data for the appropriateequation and the selective masking step information is added togetherwith the randomizer value.

-   -   The path 192 from “3” to “4” shows how a properly masked        randomizer value is directed to the mapper storage state        machine.    -   The path 192 from “4” to “2” reflects how when a new masking        step is reached in the mapper storage state machine, the system        must re-mask the randomizer values for their use in the next        step of the mapper storage state machine.

Another set of paths 194 are used to show how the mapper storage controland storage state machine accesses the external SRAM.

A path 200 is initiated when a match in the primary randomizer table hasbeen found.

-   -   The path 200 from “4” to “6” shows how the matching input value        is transferred to the microprocessor interface.    -   In circumstances where no match is encountered, that information        must be transferred to the microprocessor.

A path 198 is initiated when a value is ready for the microprocessor toread.

-   -   This path generates an interrupt to the microprocessor.    -   All necessary information regarding the match is contained in a        register.        Captured Packet Classification Description (Parallel        Microprocessor Interface)

In FIG. 19, one path 214 involves latching parallel microprocessor datainto the input register, and any appropriate data into mask captureregisters.

-   -   The system must write the parallel classification data into the        INPUT_CLASS_REG_BANKn registers. This is done indirectly by        writing into the INPUT_CLASS_VALUE register.    -   When a write to the INPUT_CLASS_REG_BANKn is to a mask register        that is being used, the system loads the parallel classification        mask register.

One set of paths 216 are initiated when the master control block startsthe parallel classification process.

-   -   When the INPUT_CLASS_WORD_COUNT exceeds the INPUT_DATA_LENGTH,        the master controller is interrupted to start the parallel        classification process.    -   The path 216 from “1” to “3” shows how the INPUT_CLASS_REG_BANKn        registers are masked with fixed enabling logic, and then mapped        and latched into the PRIM_RANDOMIZER_PAR and SEC_RANDOMIZER_PAR        registers using the optimal equation at the time.    -   The path 216 from “2” to “3” shows how the appropriate        EQn_MASK_REGm_IMP_BITx (mask impact bits) are applied based on        the selective masking step being used to generate the masked        randomizer value.    -   The path 216 from “3” to “4” shows how a properly masked        randomizer value is directed to the mapper storage state        machine.    -   The path 216 from “4” to “2” reflects how when a new masking        step is reached in the mapper storage state machine, the system        must re-mask the randomizer values for their use in the next        step of the mapper storage state machine.

Another set of paths 218 are used to show how the mapper storage controland storage state machine accesses the external SRAM.

Another path 212 is initiated when a match in the primary randomizertable has been found.

-   -   The path from “4” to “6” shows how the matching input value is        transferred to the microprocessor interface.    -   In circumstances where no match is encountered, that information        must be transferred to the microprocessor.

Another path 210 is initiated when a value is ready for themicroprocessor to read.

-   -   This path generates an interrupt to the microprocessor.    -   All necessary information regarding the match is contained in a        register.        Probability Analysis

The following analysis is used to investigate the probability of anygiven primary and secondary mapping fitting within the constraints ofmultiple values mapping to the same endpoint. The basic problem involvesthe random distribution of mapped input values across an output space ofa given size. As an example: if the output space has a size of2^16=65,536 values, and there are 10,000 random inputs, how many outputvalues are mapped to by zero, one, two, three, four, or more inputs in arandom probability analysis. This affects the chances that an individualmapping is usable, and directly impacts the number of mappings thatshould be maintained at any given time.

General Pairing (and Higher) Odds Calculations

Let us use a problem where we have ten inputs that map to outputs withthe letters A to J respectively. As we analyze the probabilities ofvarious scenarios for these odds, we use a generic number of outputvectors called “STATES” to signify the possible outputs to which anyinput can be randomly mapped. For purposes of probability analysis, apair refers to two inputs mapping to a single output, a triple refers tothree inputs mapping to a single output, and a quadruple refers to fourinputs mapping to a single output.

Odds of No Pairs

In the case of having no paired outputs, each input must be compared toall of the others. The easiest way to analyze the output situation is toshow what equalities do not occur as opposed to what equalities dooccur. In the case of outputs being equal, they could be equal becausethey are components of a pair, a triple, a quadruple, or higher. In thecases of outputs being unequal, the situation is unambiguous. In thefollowing tables, the “!=” sign is used to signify that two outputs arenot equal.

When the first output “A” is analyzed, it must be compared against allother outputs. In the comparisons for “A”, the odds that “A” is notequal to any other output are (STATES−1)/STATES because there areSTATES−1 non “A” outputs in a total of STATES outputs remaining. Whenthe second output “B” is analyzed, the “A” state has already beeneliminated. This reduces the possible remaining states to be used in theprobability calculation since there are really only STATES−1 possiblestates, of which STATES−2 do not match “B” (see Table EK below).

TABLE EK Odds of No Pairs in 10 Inputs Output Vector SituationProbability A!=B (STATES-1)/STATES A!=C (STATES-1)/STATES A!=D(STATES-1)/STATES A!=E (STATES-1)/STATES A!=F (STATES-1)/STATES A!=G(STATES-1)/STATES A!=H (STATES-1)/STATES A!=I (STATES-1)/STATES A!=J(STATES-1)/STATES B!=C (STATES-2)/(STATES-1) B!=D (STATES-2)/(STATES-1)B!=E (STATES-2)/(STATES-1) B!=F (STATES-2)/(STATES-1) B!=G(STATES-2)/(STATES-1) B!=H (STATES-2)/(STATES-1) B!=I(STATES-2)/(STATES-1) B!=J (STATES-2)/(STATES-1) C!=D(STATES-3)/(STATES-2) C!=E (STATES-3)/(STATES-2) C!=F(STATES-3)/(STATES-2) C!=G (STATES-3)/(STATES-2) C!=H(STATES-3)/(STATES-2) C!=I (STATES-3)/(STATES-2) C!=J(STATES-3)/(STATES-2) D!=E (STATES-4)/(STATES-3) D!=F(STATES-4)/(STATES-3) D!=G (STATES-4)/(STATES-3) D!=H(STATES-4)/(STATES-3) D!=I (STATES-4)/(STATES-3) D!=J(STATES-4)/(STATES-3) E!=F (STATES-5)/(STATES-4) E!=G(STATES-5)/(STATES-4) E!=H (STATES-5)/(STATES-4) E!=I(STATES-5)/(STATES-4) E!=J (STATES-5)/(STATES-4) F!=G(STATES-6)/(STATES-5) F!=H (STATES-6)/(STATES-5) F!=I(STATES-6)/(STATES-5) F!=J (STATES-6)/(STATES-5) G!=H(STATES-7)/(STATES-6) G!=I (STATES-7)/(STATES-6) G!=J(STATES-7)/(STATES-6) H!=I (STATES-8)/(STATES-7) H!=J(STATES-8)/(STATES-7) I!=J (STATES-9)/(STATES-8)Odds of Any Single Pair

When we are trying to calculate the odds of a single pair in this groupof outputs, we can do the same the same sort of a table for a singlepossibility of a pair. When we are looking at a situation where A=B, theodds can be easily determined as 1/STATES. After the odds for a singlepair are calculated, we must multiply by the number of possible pairs todetermine the total odds of any pair occurring when ten inputs aremapped into “STATES” possible outputs (see Table EK below).

TABLE EK Odds of a Single Pair Occurrence where A=B Output VectorSituation Probability A=B 1/STATES A!=C (STATES-1)/STATES A!=D(STATES-1)/STATES A!=E (STATES-1)/STATES A!=F (STATES-1)/STATES A!=G(STATES-1)/STATES A!=H (STATES-1)/STATES A!=I (STATES-1)/STATES A!=J(STATES-1)/STATES C!=D (STATES-2)/(STATES-1) C!=E (STATES-2)/(STATES-1)C!=F (STATES-2)/(STATES-1) C!=G (STATES-2)/(STATES-1) C!=H(STATES-2)/(STATES-1) C!=I (STATES-2)/(STATES-1) C!=J(STATES-2)/(STATES-1) D!=E (STATES-3)/(STATES-2) D!=F(STATES-3)/(STATES-2) D!=G (STATES-3)/(STATES-2) D!=H(STATES-3)/(STATES-2) D!=I (STATES-3)/(STATES-2) D!=J(STATES-3)/(STATES-2) E!=F (STATES-4)/(STATES-3) E!=G(STATES-4)/(STATES-3) E!=H (STATES-4)/(STATES-3) E!=I(STATES-4)/(STATES-3) E!=J (STATES-4)/(STATES-3) F!=G(STATES-5)/(STATES-4) F!=H (STATES-5)/(STATES-4) F!=I(STATES-5)/(STATES-4) F!=J (STATES-5)/(STATES-4) G!=H(STATES-6)/(STATES-5) G!=I (STATES-6)/(STATES-5) G!=J(STATES-6)/(STATES-5) H!=I (STATES-7)/(STATES-6) H!=J(STATES-7)/(STATES-6) I!=J (STATES-8)/(STATES-7)

To determine the overall odds, the total number of possible pairs mustbe calculated. A binomial equation for probability provide us with thetotal number of pairs in ten outputs.

Binomial Equation:

$\left( \frac{n}{m} \right) = \frac{n!}{{\left( {n - m} \right)!}*{m!}}$

In the case where n=2 and m=10, referred to as 2 choose 10, the binomialequation above produces a result of 45 possible combinations of a singlepair in ten output values.

Odds of Any Single Triple

When we are trying to calculate the odds of a single triple, we arelooking at a situation where A=B=C. The odds can for a single occurrencecan be easily determined as (1/STATES)*(1/STATES). After the odds for asingle triple are calculated, we must multiply by the number of possibletriples to determine the total odds of a any triple occurring when 10inputs are mapped into “STATES” possible outputs (see Table EL below).

TABLE EL Odds of a Single Triple Occurrence where A=B=C Output VectorSituation Probability A=B 1/STATES A=C 1/STATES A!=D (STATES-1)/STATESA!=E (STATES-1)/STATES A!=F (STATES-1)/STATES A!=G (STATES-1)/STATESA!=H (STATES-1)/STATES A!=I (STATES-1)/STATES A!=J (STATES-1)/STATESD!=E (STATES-2)/(STATES-1) D!=F (STATES-2)/(STATES-1) D!=G(STATES-2)/(STATES-1) D!=H (STATES-2)/(STATES-1) D!=I(STATES-2)/(STATES-1) D!=J (STATES-2)/(STATES-1) E!=F(STATES-3)/(STATES-2) E!=G (STATES-3)/(STATES-2) E!=H(STATES-3)/(STATES-2) E!=I (STATES-3)/(STATES-2) E!=J(STATES-3)/(STATES-2) F!=G (STATES-4)/(STATES-3) F!=H(STATES-4)/(STATES-3) F!=I (STATES-4)/(STATES-3) F!=J(STATES-4)/(STATES-3) G!=H (STATES-5)/(STATES-4) G!=I(STATES-5)/(STATES-4) G!=J (STATES-5)/(STATES-4) H!=I(STATES-6)/(STATES-5) H!=J (STATES-6)/(STATES-5) I!=J(STATES-7)/(STATES-6)

The binomial equation for n=3, m=10 provides a total of 120 possibletriples given ten possible output values. The odds for the single triplemust be multiplied by 120 to get the overall odds for all cases of asingle triple.

Odds of Any Single Quadruple

When we are trying to calculate the odds of a single quadruple, we arelooking at a situation where A=B=C=D. The odds can for a singleoccurrence can be easily determined as (1/STATES)*(1/STATES)*(1/STATES).After the odds for a single quadruple are calculated, we must multiplyby the number of possible quadruples to determine the total odds of anyquadruple occurring when ten inputs are mapped into “STATES” possibleoutputs (see Table EM below).

TABLE EM Odds of a Single quadruple Occurrence where A=B=C Output VectorSituation Probability A=B 1/STATES A=C 1/STATES A=D 1/STATES A!=E(STATES-1)/STATES A!=F (STATES-1)/STATES A!=G (STATES-1)/STATES A!=H(STATES-1)/STATES A!=I (STATES-1)/STATES A!=J (STATES-1)/STATES E!=F(STATES-2)/(STATES-1) E!=G (STATES-2)/(STATES-1) E!=H(STATES-2)/(STATES-1) E!=I (STATES-2)/(STATES-1) E!=J(STATES-2)/(STATES-1) F!=G (STATES-3)/(STATES-2) F!=H(STATES-3)/(STATES-2) F!=I (STATES-3)/(STATES-2) F!=J(STATES-3)/(STATES-2) G!=H (STATES-4)/(STATES-3) G!=I(STATES-4)/(STATES-3) G!=J (STATES-4)/STATES-3) H!=I(STATES-5)/(STATES-4) H!=J (STATES-5)/(STATES-4) I!=J(STATES-6)/(STATES-5)

The binomial equation for n=4, m=10 provides a total of 210 possiblequadruples given ten possible output values. The odds for the singlequadruple must be multiplied by 210 to get the overall odds for allcases of a single quadruple.

Odds of Pair and a Triple:

When we are trying to calculate the odds of a single pair where A=B, anda single triple where C=D=E, the odds are more complex. The odds for thesingle pair are (1/STATES), and the odds for the single triple are(1/STATES)*(1/STATES). All of the remaining inputs must not pair witheither the output from the pair (A) or the output from the triple (C)(see Table EN below).

TABLE EN Odds of a Single Pair A=B and a Single Triple C=D=E OutputVector Situation Probability A=B 1/STATES (PAIR) C=D 1/STATES (TRIPLE)C=E 1/STATES (TRIPLE) A!=C (STATES-1)/STATES A!=F (STATES-1)/STATES A!=G(STATES-1)/STATES A!=H (STATES-1)/STATES A!=I (STATES-1)/STATES A!=J(STATES-1)/STATES F!=G (STATES-2)/(STATES-1) F!=H (STATES-2)/(STATES-1)F!=I (STATES-2)/(STATES-1) F!=J (STATES-2)/(STATES-1) G!=H(STATES-3)/(STATES-2) G!=I (STATES-3)/(STATES-2) G!=J(STATES-3)/(STATES-2) H!=I (STATES-4)/(STATES-3) H!=J(STATES-4)/(STATES-3) I!=J (STATES-5)/(STATES-4)

The calculation of the number of possible occurrences of a single pairand a single triple are slightly harder. For each possible pair, thereare eight remaining outputs that can generate a triple. Similarly, foreach possible triple, there are seven possible outputs remaining thatcan generate a pair. Approaching this problem from either side willproduce the same answer.

Binomial Equation:

$\left( \frac{n}{m} \right) = \frac{n!}{{\left( {n - m} \right)!}*{m!}}$

Total Possibility Calculation for a Single Pair and a Single Triple:

${\left( \frac{2}{10} \right)*\left( \frac{3}{8} \right)} = 2520$General Formula Development

By reviewing the above tables for “No Pairs”, “Single Pair”, “SingleTriple”, “Single quadruple”, and “Single Pair and Single Triple”, it ispossible to develop a generic formula to calculate the probability. Thefirst term in the formula accounts for the pairs, triples andquadruples. This term accounts for the (1/STATES) terms for all of thepossible outputs that are paired.

${{Match}\mspace{14mu}{Term}} = \left( \frac{1}{STATES} \right)^{({{Pairs} + {2^{*}{Triples}} + {3^{*}{Quadruples}}})}$

Once the pairs, triples, and quadruples have been accounted for, all ofthe appropriate outputs must be checked to make sure they do not matchany other output. One element from each pair, triple and quadruple mustbe checked against one element from all remaining pairs, triples, andquadruples in addition to the remaining un-matched outputs. Allremaining un-matched outputs must also be checked against each other toverify that they do not match. The UNMATCHED_OUTPUTS−1 term accounts forthe fact that with n outputs, there are only n−1 checks to be done withthe first one.

${{Non\_ Match}{\_ Term}} = {\prod\limits_{m = 0}^{\{{{UNMATCHED\_ OUTPUTS} - 1}\}}\left( \frac{{STATES} - 1 - m}{{STATES} - m} \right)^{\{{{UNMATCHED\_ OUTPUTS} - m}\}}}$UNMATCHED_OUTPUTS=INPUTS−1−PAIRS−2*TRIPLES−3*QUADRUPLESOccurrence_Probability=Match_Term*Non_Match_TermOverall Odds forPair/Triple/QuadrupleSituation=#Occurrences*Occurrence_ProbabilityCalculation of Number of Occurrences

The number of occurrences (combo_hits) for any given combination ofpairs, triples, and quadruples is calculated in a sequential form. Theproblem can be broken down first into calculating the combinations ofquadruples within the space of inputs, then by subtracting out theinputs associated with quadruples and calculating the combinations oftriples within the remaining space of inputs, and finally by subtractingout the inputs associated with quadruples and triples, and calculatingthe combinations of pairs within the remaining space of inputs. Thecombination values for pairs, triples and quadruples can be multipliedtogether to determine the overall odds for a specific combination ofthese elements.

The following examples show empirically how this is done, and show thederivation of the formulas for pairs and triples.

Explanation of Combo_hits Pair Calculation for 10 Inputs

The number of possibilities is based purely upon the number of inputsthat are present. If there are ten inputs, there are (10 choose 2)=45possible pairs in ten inputs. Once the first pair is gone, there are (8choose 2)=28 chances of selecting a second pair from the remaininginputs. Once the second pair is gone, there are (6 choose 2)=15 chancesof selecting a third pair from the remaining inputs.

Given 45 possible pairs, there are (45 choose 3)=14190 combinations ofthree pairs out of 45 possible pairs.

The odds for the first pair are 45/45, the odds for the second pair tobe non-overlapping are 28/44, and the odds for the third pair to benon-overlapping are 15/43.

Pair Example for 10 Inputs

If there are enough inputs left to make a pair:

-   #1 Possible_Pairs=N_Choose_M (in    puts−3*(triple_count)−2*(pair_Count−1 ),2) Check remaining Inputs,    How many possible pairs can be found.-   #2 Possible_Pairs/=(Total_pairs-(pair_count−1))-   #3 Running_Pair_Hits*=Possible_Pairs-   #4 Combo_Hits=Running_Pair_Hits *N_Choose_M(Total_Pairs, Pair_count)

TABLE EO Example of ten Inputs and up to five pairs: Total_Pairs =N_Choose_M(10,2) = 45 Running_Pair_Hits = 1 Step #3 Step #1 Step #2Running_(—) Step #4 Step Possible Pairs 2 Pairs Pair_Hits Combo_Hits NoN/A N/A 1 1 Pairs 1 10 Choose 2 /45 =1 1*(45 Choose 1) =45 =1 =45 2 8Choose 2 /44 =0.636363 0.63*(45 Choose 2) =28 =0.636363 =0.63*990 =630 36 Choose 2 /43 =0.221987 0.22*(45 Choose 3) =15 =0.348837 =0.22*14190=3150 4 4 Choose 2 /42 =0.031712 0.031*(45 Choose 4) =6 =0.142857=0.031*148995 =4725 5 2 Choose 2 /41 =0.0007735 0.00073*(45 Ch. 5) =1=0.02439 =0.00073*1221759 =945

Test for five pairs:

-   {(10 Choose 2)/Total_Pairs}*{(8 Choose 2)/(Total_Pairs−1)}*{(6    Choose 2)/(Total_Pairs−2)}*-   {(4 Choose 2)/(Total_Pairs−3)}*{(2 Choose 2)/(Total_Pairs−4)}

${running\_ hits} = {\frac{10!}{{\left( {10 - 2} \right)!}*{2!}}*\frac{8!}{{\left( {8 - 2} \right)!}*{2!}}*\frac{6!}{{\left( {6 - 2} \right)!}*{2!}}*\frac{4!}{{\left( {4 - 2} \right)!}*{2!}}*\frac{2!}{{\left( {2 - 2} \right)!}*{2!}}\frac{\left( {{total\_ pairs} - {pairs}} \right)!}{({total\_ pairs})!}}$

${running\_ hits} = {\frac{{inputs}!}{\left( {{inputs} - {2*{pairs}}} \right)!}*\frac{1}{{2!}^{pairs}}*\frac{\left( {{total\_ pairs} - {pairs}} \right)!}{({total\_ pairs})!}}$

${combo\_ hits} = {\frac{{inputs}!}{\left( {{inputs} - {2*{pairs}}} \right)!}*\frac{1}{{2!}^{pairs}}*\frac{\left( {{total\_ pairs} - {pairs}} \right)!}{({total\_ pairs})!}*\frac{({total\_ pairs})!}{{\left( {{total\_ pairs} - {pairs}} \right)!}*{{pairs}!}}}$

${{combo\_ hits}{\_ for}{\_ pairs}} = {\frac{{inputs}!}{\left( {{inputs} - {2*{pairs}}} \right)!}*\frac{1}{{2!}^{pairs}}*\frac{1}{{pairs}!}}$Triple Example for Fifteen Inputs

If there are enough inputs left to make a triple:

-   #1 Possible_Triples=N_Choose_M(inputs−3*(triple_count−1),3) Check    remaining Inputs, How many possible triples can be found.-   #2 Possible_Triples/=(Total_triples-(triple_count−1))-   #3 Running_Triple_Hits*=Possible_Triples-   #4 Combo_Hits=Running_Triple_Hits *N_Choose_M(Total_Triples,    Triple_count)-   Total_triples=N_Choose_M(15,3)=455-   Running_Triple_Hits=1

TABLE EP Example of fifteen inputs and up to five triples Step #1 Step#2 Step #3 Possible Divide by Running_(—) Step #4 Step Triples TotalTrips Triple_Hits Combo_Hits No N/A N/A 1 1 Triples 1 15 Choose 3 /455=1 1*(455 Choose 1) =455 =1 =455 2 12 Choose 3 /454 =0.4846 0.4846*(455=220 =0.4846 Choose 2) =0.4846*103285 =50050 3 9 Choose 3 /453 =0.08980.0898*(455 =84 =0.1854 Choose 3) =0.0898*15596035 =1401400 4 6 Choose 3/452 =0.00397 0.00397*(455 =20 =0.04424 Choose 4) =0.00397*1762351 955=7007000 5 3 Choose 3 /451 =8.8158e−6 8.8158e−6*(455 =1 =0.02217 Ch. 5)=8.8158e− 6*158964146341 =1401400

Test for five triples:

-   {(15 Choose 3)/Total_Trips}*{(12 Choose 3)/(Total_Trip−1)}*{(9    Choose 3)/(Total_Trips−2)}*-   {(6 Choose 3)/(Total_Trips−3)}*{(3 Choose 3)/(Total_Trips−4)}

${running\_ hits} = {\frac{15!}{{\left( {15 - 3} \right)!}*{3!}}*\frac{12!}{{\left( {12 - 3} \right)!}*{3!}}*\frac{9!}{{\left( {9 - 3} \right)!}*{3!}}*\frac{6!}{{\left( {6 - 3} \right)!}*{3!}}*\frac{3!}{{\left( {3 - 3} \right)!}*{3!}}\frac{\left( {{total\_ triples} - {triples}} \right)!}{({total\_ triples})!}}$

${running\_ hits} = {\frac{{inputs}!}{\left( {{inputs} - {3*{triples}}} \right)!}*\frac{1}{{3!}^{triples}}*\frac{\left( {{total\_ triples} - {triples}} \right)!}{({total\_ triples})!}}$

${combo\_ hits} = {\frac{{inputs}!}{\left( {{inputs} - {3*{triples}}} \right)!}*\frac{1}{{3!}^{triples}}*\frac{\left( {{total\_ triples} - {triples}} \right)!}{({total\_ triples})!}*\frac{({total\_ triples})!}{{\left( {{total\_ triples} - {triples}} \right)!}*{{triples}!}}}$

${{combo\_ hits}{\_ triples}} = {\frac{{inputs}!}{\left( {{inputs} - {3*{triples}}} \right)!}*\frac{1}{{3!}^{triples}}*\frac{1}{{triples}!}}$Quadruple Example for 20 Inputs:

If there are enough inputs left to make a quadruple:

-   #1 Possible_quadruples=N_Choose_M(inputs−4*(quadruple_count−1),4)    Check remaining Inputs, How many possible quadruples can be found.-   #2 Possible_quadruples/=(Total_quadruples-(quadruple_count−1))-   #3 Running_quadruple_Hits*=Possible_quadruples-   #4 Combo_Hits=Running_quadruple Hits *N_Choose_M(Total_quadruples,    quadruple_count)

TABLE EQ Example of twenty inputs and up five quadruplesTotal_quadruples = N_Choose_M(20,4) = 4845 Running_Triple_Hits=1 Step #1Step #2 Step #3 Possible Divide by Running_(—) Step #4 Step quadruplesTotal Quads Quad_Hits Combo_Hits No N/A N/A 1 1 Quads 1 20 Choose 4/4845 =1 1*(4845 Choose 1) =4845 =1 =4845 2 16 Choose 4 /4844 =0.37570.3757*(4845 =1820 =0.3757 Choose 2) =0.3757*11734590 4408685 3 12Choose 4 /4843 =0.038402 0.0384*(4845 =495 =0.1022 Choose 3)=0.0384*18943539 790 =727476750 4 8 Choose 4 /4842 =0.0005550.000555*(4845 =70 =0.014457 Choose 4) =0.000555*229311 54915795=12730843125 5 4 Choose 4 /4841 =1.146E−7 1.146E−7*(4845 =1 =0.000207Ch. 5) =8.8158e− 6*22201944189472 700 =2546168625

Test for five quadruples:

-   {(20 Choose 4)/Total_Quads}*{(16 Choose 4)/(Total_Quads−1)}*{(12    Choose 4)/(Total_Quads−2)}*-   {(8 Choose 4)/(Total_Quads−3)}*{(4 Choose 4)/(Total_Quads−4)}

${running\_ hits} = {\frac{20!}{{\left( {20 - 4} \right)!}*{4!}}*\frac{16!}{{\left( {16 - 4} \right)!}*{4!}}*\frac{12!}{{\left( {12 - 4} \right)!}*{4!}}*\frac{8!}{{\left( {8 - 4} \right)!}*{4!}}*\frac{4!}{{\left( {4 - 4} \right)!}*{3!}}*\frac{\left( {{total\_ quads} - {quads}} \right)!}{({total\_ quads})!}}$

${running\_ hits} = {\frac{{inputs}!}{\left( {{inputs} - {4*{quads}}} \right)!}*\frac{1}{{4!}^{quadruples}}*\frac{\left( {{total\_ quads} - {quads}} \right)!}{({total\_ quads})!}}$

${combo\_ hits} = {\frac{{inputs}!}{\left( {{inputs} - {4*{quads}}} \right)!}*\frac{1}{{4!}^{tquadruples}}*\frac{\left( {{total\_ quads} - {quads}} \right)!}{({total\_ quads})}*\frac{({total\_ quads})!}{{\left( {{total\_ quads} - {quads}} \right)!}*{{quads}!}}}$

${{combo\_ hits}{\_ quadruples}} = {\frac{{inputs}!}{\left( {{inputs} - {4*{quads}}} \right)!}*\frac{1}{{4!}^{quadruples}}*\frac{1}{{quadruples}!}}$Multiple Table AnalysisIntroduction

The following analysis is used to evaluate the odds that variouscombinations of multiple tables will be sufficient for handling all ofthe pairs, triples and quadruples that may arise. The issue is what theodds are that any given equation will be handled properly by the tablesthat are available. If this overall odds for any random equation is toolow, then it will be necessary to store mappings for more equations andto be able to swap equations more frequently.

Primary Randomizer Simulations for Various Scenarios

The following Primary Randomizer simulations were run for 10,000 inputsand 65,536 states. The goal of these simulations was to show whatprobability of success could be achieved by permitting a certain numberof pairs, triples and quadruples of Primary Randomizer values.

Maximize Pairs, and Vary Triples with No Quadruples 1024 Pairs, 0Triples, 0 Quadruples 5.49e−16 1024 Pairs, 8 Triples, 0 Quadruples3.30e−8 1024 Pairs, 16 Triples, 0 Quadruples 1.59e−4 1024 Pairs, 24Triples, 0 Quadruples 0.014 1024 Pairs, 32 Triples, 0 Quadruples 0.1211024 Pairs, 40 Triples, 0 Quadruples 0.240 1024 Pairs, 48 Triples, 0Quadruples 0.268 1024 Pairs, 56 Triples, 0 Quadruples 0.269

This experiment shows that allowing more than 48 Triples seems toproduce minimal impact.

Use 48 Triples, and Vary Pairs with No Quadruples 128 Pairs, 48 Triples,0 Quadruples 2.6895e−168 256 Pairs, 48 Triples, 0 Quadruples 1.7762e−87384 Pairs, 48 Triples, 0 Quadruples 9.8751e−39 512 Pairs, 48 Triples, 0Quadruples 6.6245e−12 640 Pairs, 48 Triples, 0 Quadruples 0.067 768Pairs, 48 Triples, 0 Quadruples 0.268 896 Pairs, 48 Triples, 0Quadruples 0.268 1024 Pairs, 48 Triples, 0 Quadruples 0.268

This experiment shows that allowing more than 768 Pairs seems to produceminimal impact.

Use 896 Pairs, 48 Triples, and Vary Quadruples 896 Pairs, 48 Triples, 0Quadruples 0.268 896 Pairs, 48 Triples, 1 Quadruple 0.609 896 Pairs, 48Triples, 2 Quadruples 0.826 896 Pairs, 48 Triples, 3 Quadruples 0.917896 Pairs, 48 Triples, 4 Quadruples 0.946 896 Pairs, 48 Triples, 5Quadruples 0.954

This experiment shows that allowing more than 5 Quadruples seems toproduce minimal impact.

Primary Randomizer Simulation Conclusions

The above experiments show that for the example of 65,536 States and10,000 inputs, there is a better than 95% chance that a PrimaryRandomizer equation value will produce no more than 896 Pairs, 48Triples, 5 Quadruples. By permitting 1024 Multiple Entries, that can bepairs, triples or quadruples, the odds of a successful PrimaryRandomizer will therefore be better than 95%.

Secondary Randomizer Probability Analysis

Introduction

Once the Primary Randomizer spreads out the inputs across the memoryspace, the job of the Secondary Randomizer is to differentiate betweenany paired, tripled or quadrupled inputs. The probability analysis forthis function is much different than for the Primary Randomizer. Forease of analysis, worst case Primary Randomizer distributions can beused instead of weighting the values for all possible situations.

Pairs

In the case of a Primary Randomizer Pair, the odds that the uncorrelatedSecondary Randomizer values will be the same can be calculated asfollows:

${{Odds\_ Pair}{\_ Has}{\_ No}{\_ Match}} = \frac{{STATES} - 1}{STATES}$

In the case of a Pair, this is a straightforward probability where thereare (STATES−1) out of (STATES) values for the second SecondaryRandomizer Value that will not be a match.

Triples

In the case of a Triple with three Secondary Randomizer Values labeledA, B, and C, there are a number of odds that must be included. There arethree individual possibilities that must be considered where A=B, B=G orA=C. Any of these could individually destroy the usability of theTriple, and they include the odds of all three being the same.

${{Odds\_ Triple}{\_ A}{\_ Equals}{\_ B}} = \frac{1}{STATES}$${{Odds\_ Triple}{\_ Has}{\_ Match}} = \frac{3}{STATES}$${{Odds\_ Triple}{\_ Has}{\_ No}{\_ Match}} = {1 - \frac{3}{STATES}}$${{Odds\_ Triple}{\_ Has}{\_ No}{\_ Match}} = \frac{{STATES} - 3}{STATES}$Quadruples

In the case of a Quadruple, with four Secondary Randomizer Valueslabeled A, B, C and D, there are a number of odds that must be included.There are six possible cases of a pair: A=B, A=C, A=D, B=C, B=D, andC=D.

${{Odds\_ Quadruple}{\_ A}{\_ Equals}{\_ B}} = \frac{1}{STATES}$${{Odds\_ Quadruple}{\_ Has}{\_ Match}} = \frac{6}{STATES}$${{Odds\_ Quadruple}{\_ Has}{\_ No}{\_ Match}} = {1 - \frac{6}{STATES}}$${{Odds\_ Quadruple}{\_ Has}{\_ No}{\_ Match}} = \frac{{STATES} - 6}{STATES}$Overall Secondary Randomizer Odds

In a case with a number of Pairs, Triples and Quadruples, the followingformula can be used to determine the Overall Odds that the SecondaryRandomizer will differentiate all Pairs, Triples and Quadruples.Odds_Good_SR=Odds Pair_Has_No_Match^(Number) ^(—) ^(Pairs)*Odds_Triple_Has_No_Match^(Number) ^(—) ^(Triples)*Odds_Quadruple_Has_No_Match^(Number) ^(—) ^(Quadruples)Secondary Randomizer Example

For an example case of 65536 States, with 896 Pairs, 48 Triples, and 5Quadruples, the odds that the Secondary Randomizer values will not beduplicated for any of the pairs, triples or quadruples can be calculatedas follows:

${\_ SR} = {\left( \frac{{STATES} - 1}{STATES} \right)^{896}*\left( \frac{{STATES} - 3}{STATES} \right)^{48}*\left( \frac{{STATES} - 6}{STATES} \right)^{5}}$Odds_Good_SR=0.983445

In this example, there is a greater than 98% chance that the SecondaryRandomizer will differentiate all of the pairs, triples, and quadruples.It should be noted that the odds that 896 pairs, 48 triples and 5quadruples will be needed are very slim. In the average case, the oddsthat the Secondary Randomizer will be usable will be much improved.

Feedback Shift Register Theory

The purpose of this discussion is to explain the basics of serial shiftregister theory, and how those apply to the system. The areas that areanalyzed include basic feedback shift register operation, future stateprediction, shift register time acceleration, and masking of inputvalues. A four bit feedback shift register is used to explain the theorybehind the system (see FIG. 20).

Basic Feedback Shift Register Theory

An exemplary basic feedback shift register contains four D-flip flopsthat are clocked simultaneously. Each of these flip flops is also knownas a stage in the shift register. With four stages, the shift registerhas 2^4=16 possible states. In the case of the shift register in thisexample, the Q2 and Q3 stages are fed back to generate the first stageQ0 in conjunction with the INPUT value. This feedback mechanism occurscontinuously for each clock of the CLOCK signal, and results in thevalues of Q0–Q3 cycling through a pattern that depends upon theirinitial state as well as the pattern of INPUTs that are applied.

Equations For Each Shift Register Stage

The next value of each shift register stage, i.e. Q0+, Q1+, Q2+ and Q3+,can be calculated as a function of both the present values of all shiftregister stages, i.e. Q0, Q1, Q2 and Q3, and the value of the INPUT.

-   -   Shift Register Equations        Q0+=((INPUT) XOR (Q2 XOR Q3))        Q1+=Q0        Q2+=Q1        Q3+=Q2        Features of XOR Gates and XORTrees

A 2-input XOR gate produces an output of “1” when it's inputs aredifferent. If a 2-input XOR gate's inputs are the same, it produces andoutput of “0”. When more than two inputs are XOR'd together, the outputis a “1” if there are an odd number of inputs that are “1”s and theoutput is a “0” if there are zero or an even number of inputs that are“1” (see Table ER below).

TABLE ER XOR Gate Logic Truth Table Input 1 Input 2 Output 0 0 0 0 1 1 10 1 1 1 0

From the XOR logic truth table, it can be seen that the for an value“A”, the XOR of “A” and “A” equals “0”. This results because whether “A”is a 0 or a 1, when “A” is XOR'd with itself, the output is a zero. Thisfeature is critical when evaluating shift registers over time.

Shift Register State Prediction

As a shift register is clocked along, the feedback continues tointroduce values back into the input stage. In some cases, these cancelout terms that exist due to the fact that “A” XOR “A” =0. In othercases, terms continue to propagate. For purposes of description, thesequence of inputs that are applied to the shift register areA,B,C,D,E,F,G,H,J,K,L,M,N. In this example, the initial state is assumedto be Q0=Q0S, Q1=Q1S, Q2=Q2S, and Q3=Q3S to signify that these arestarting values. For description purposes, the XOR of multiple inputsare XOR(a,b,c, . . . z). In Table ES shown below, terms that arecanceled out for a specific stage after a specific input are not shown.

TABLE ES Shift Register State Prediction Input Q0 Value Q1 Value Q2Value Q3 Value Q0S Q1S Q2S Q3S A XOR(A,Q2S,Q3S) Q0S Q1S Q2S BXOR(B,Q1S,Q2S) XOR(A,Q2S,Q3S) Q0S Q1S C XOR(C,Q0S,Q1S) XOR(B,Q1S,Q2S)XOR(A,Q2S,Q3S) Q0S D XOR(A,D,Q0S,Q2S, XOR(C,Q0S,Q1S) XOR(B,Q1S,Q2S)XOR(A,Q2S, Q3S) Q3S) E XOR(A,B,E,Q1S,Q3S) XOR(A,D,Q0S,Q2S,Q3S)XOR(C,Q0S,Q1S) XOR(B,Q1S, Q2S) F XOR(B,C,F,Q0S,Q2S) XOR(A,B,E,Q1S,Q3S)XOR(A,D,Q0S, XOR(C,Q0S, Q2S,Q3S) Q1S) G XOR(A,C,D,G,Q1S,Q2S,XOR(B,C,F,Q0S,Q2S) XOR(A,B,E,Q1S, XOR(A,D, Q3S) Q3S) Q0S,Q2S, Q3S) HXOR(B,D,E,H,Q0S,Q1S, XOR(A,C,D,G,Q1S,Q2S, XOR(B,C,F,Q0S, XOR(A,B, Q3S)Q3S) Q2S) E,Q1S,Q3S) J XOR(A,C,E,F,J, XOR(B,D,E,H, XOR(A,C,D,G, XOR(B,C,Q0S,Q1S,Q2S,Q3S) Q0S,Q1S,Q3S) Q1S,Q2S,Q3S) F, Q0S,Q2S) K XOR(A,B,D,F,G,KXOR(A,C,E,F,J, XOR(B,D,E,H, XOR(A,C, Q0S,Q1S,Q3S) Q0S,Q1S,Q2S,Q3S)Q0S,Q1S,Q3S) D,G, Q1S,Q2S, Q3S) L XOR(A,B,C,E,G,H,L XOR(A,B,D,F,G,K,XOR(A,C,E,F,J, XOR(B,D, Q0S,Q2S) Q0S,Q1S,Q3S) Q0S,Q1S,Q2S, E,H, Q3S)Q0S,Q1S, Q3S) M XOR(A,B,C,D,F,H,J, XOR(A,B,C,E,G,H,L XOR(A,B,D,F,G,XOR(A,C, M,Q2S) Q0S,Q2S) K, E,F,J, Q0S,Q1S,Q3S) Q0S,Q1S, Q2S,Q3S) NXOR(B,C,D,E,G,J,K,N XOR(A,B,C,D,F,H,J,M, XOR(A,B,C,E,G, XOR(A,B, Q2S)Q2S) H,L D,F,G,K, Q0S,Q2S) Q0S,Q1S, Q3S)

From a theoretical standpoint, the exemplary shift register could beused to map inputs A,B,C,D,E,F,G,H,J,K,L,M, and N to a 4 bit valueconsisting of Q0, Q1, Q2 and Q3. Theoretically, after a shift registerhas been clocked through some number of cycles (thirteen in this case),the output can be predicted exactly by knowing what the inputs were andwhat the initial condition was. In the case of the system, therandomizers in the data framer ASIC are initialized to all 0's prior tothe start of the packet. This removes the Q0S, Q1S, Q2S, and Q3S termsfrom the analysis since they are 0^(i). By doing this, the state of eachstage becomes an XOR tree of a set of inputs.

The system could allow the randomizer to start at any value at the startof the packet. In that case, the value of the randomizer at the start ofthe packet would have to be captured and factored out of the finalresult. The mapped effects of the initial condition would have to besubtracted out of the final randomizer numbers knowing what the initialconditions were. This approach is similar to the masking approaches usedin the system.

In the case of Table ES, Q0 after thirteen cycles is the XOR of inputsB,C,D,E,G,J,K and N. This XOR function can be implemented in a tree ofXOR gates to generate the value. The values of Q1, Q2, and Q3 can becalculated using similar trees of XOR gates that use the inputs found intheir specific equation.

By viewing Table ES, it can be seen that the XOR terms for a specificstage such as Q0 vary from clock cycle to clock cycle. Instead ofproviding length variability by attempting to calculate these trees foreach length (which would be extremely prohibitive in size), the systemuses a fixed length of inputs in its equation generators regardless ofthe end user length selection. The system relies on the fact that a “0”value input does not appear in the output state vectors, other than inthe shifting of the state register that it introduces.

Time Acceleration Theory

To produce a general purpose ASIC, the system implements a large numberof possible input values (1024). This large fixed value allows a singleset of XOR trees to be implemented to calculate the state values foreach equation. The result is that in most situations, the input valuesthat the user is classifying are padded with trailing “0” values. Inmany applications, users may wish to classify only 50 to 100 possibleinputs. In the data framer ASIC, the randomizers could continue to cycle“0” values into the randomizers, after the bits of interest, to reach afinal value of 1024 that is used to generate all equation values. Thisresults in added time delay, and additional power consumption in thehigh speed data framer. As an alternative, a feature called timeacceleration is used.

If a feedback shift register, is applied a sequence of “0”s prior tobeing disabled, the final output state is a predictable value based onthe state prior to the start of the shifting in of “0”s, and the numberof “0”s that are shifted in. In Table ES, this can be viewed as havingan initial state and then having all “0” inputs. In this case, theoutput vector after some number of cycles is purely a functionalre-mapping through an XOR tree of the initial state. To provideflexibility, a set of binary weighted shifters are implemented. Thispermits from 1 to 1023 trailing zeros to be effectively simulated by thetime accelerator.

As an example of how the successive binary weighting would work, TableES can be used to show how values are mapped to generate differentweightings for shifting 0's. In the case of Table ET below, each shiftis determined by looking at the table above and removing all of theInput values because these are each 0. The values listed Table ET belowreflect how a starting value of Q0S, Q1S, Q2S, Q3S is mapped after “n”cycles of “0” inputs.

TABLE ET Binary Weighted “0” Input Shifts Number of Zeros Q0 Value Q1Value Q2 Value Q3 Value 1 XOR(Q2S,Q3S) XOR(Q0S) XOR(Q1S) XOR(Q2S) 2XOR(Q1S,Q2S) XOR(Q2S,Q3S) XOR(Q0S) XOR(Q1S) 4 XOR(Q0S,Q2S,Q3S)XOR(Q0S,Q1S) XOR(Q1S,Q2S) XOR(Q2S,Q3S)

The time acceleration approach involves selectively and serially mappingthe inputs through a number of binary weighted “0” input shift stages togenerate an output. For example purposes, a starting vector of Q0S, Q1S,Q2S, and Q3S are first mapped through a “0” input shift length of one.The result is then mapped through a “0” input shift length of two. Thatresult is then mapped through a “0” input shift length of four. Theresult after mapping through shift lengths of 1, 2, and 4 should thenequal a result as though we started with Table ES above and had sevencycles of inputs that were equal to “0” (see Table EU below).

TABLE EU Mapping Through various Shift Lengths Number of Zeros Q0 ValueQ1 Value Q2 Value Q3 Value 0=Start Q0S Q1S Q2S Q3S 1 XOR(Q2S,Q3S)XOR(Q0S) XOR(Q1S) XOR(Q2S) 2 XOR(Q0S, XOR(Q1S, XOR(Q2S,Q3S) XOR(Q0S)Q1S) Q2S) 4 XOR(Q0S,Q1S, XOR(Q0S,Q1S, XOR(Q1S,Q2S, XOR(Q2S,Q3S, Q2S,Q3S,Q1S,Q2S)= Q2S, Q0S)= Q0S)= XOR(Q0S,Q2S) Q3S)= XOR(Q0S,Q2S,Q3S)XOR(Q1S,Q2S,Q3S) XOR(Q1S,Q3S)

When comparing with Table ES above, for the INPUT G row, and zeroing outinputs A–G, we can see that the mapping is equivalent to the tableimmediately above after a total shift of 1,2 and 4 zero inputs. Thisdisplays how a variable time accelerated value can be rapidly calculatedfor a given equation.

Masking Theory

Referring to Table ES above, it can be seen that every input bit appearsin an XOR tree term for one or more of the shift register output bits.As described earlier, if an input is XOR'd with itself, the result is avalue of “0”. Therefore, if a final shift register output is known thatincluded a specific input in its calculations, that input can be removedby XOR'ing each bit in the result with that specific input bit, if thatinput bit affected the final shift register output (see Table EV below).

TABLE EV Copied from the Table ES above Input Q0 Value Q1 Value Q2 ValueQ3 Value N XOR(B, C, D, XOR(A, B, C, XOR(A, B, C, XOR(A, B, D, E, G, J,K, N D, F, H, J, M, E, G, H, L F, G, K, Q0S, Q2S) Q2S) Q0S, Q2S) Q1S,Q3S)

In this case, if we wish to selectively mask out INPUT E from theresult, we would XOR input E in with the Q0 and the Q2 bits. Theselective masking approach in the system relies on the theory of knowingand subtracting out the effects of specific inputs. For any given Inputbit that is desired to be masked out, it is possible to determine whichbits in the output result are affected by the input bit. This is done byusing the input mapper, for a specific equation, and sets the initialstate of the randomizer to all “0”s, while controlling all inputs inparallel simultaneously. The process is done through a walking onespattern that takes the bit under investigation and sets it to a “1”,while setting all other bits to a “0”. As each bit that is analyzed isset to a 1, the mapper outputs are stored in bit locations referred toas mask impact bits. The system allows the user to decide selectivelywhat bits must be masked, versus those that can be always analyzed, orthose that are never viewed.

Explanation of Masking Effect

The effect of masking is to remove an input from consideration in theanalysis. This removal effectively makes the input appear as though itwas a 0 and had no affect on the final shift register output. Therefore,there is no difference between a masked input and one that sets all ofthe masked bits to zero. In the following example of three inputs andtheir various combinations, input B is masked. The like shaded rows areequivalent as a result of this masking (see Table EW below).

TABLE EW Masking Effect Input A

Input C 0 0 0

0 1 0

1 0 0

1 1 0

Sequential Masking

A two step masking operation could be done as follows: first inputs Aand B are masked and we differentiate based on input C. If input C isfound to be a 0, then input B is masked and we differentiate on input A.If input C is found to be a 1, then input A is masked and wedifferentiate on input B (see Table EX-EZ below).

TABLE EX Masking Step #1 (Inputs A and B Masked) Post Masked Input AMasked Input B Input C MaskingValue 0 0 0 0, 0, 0 0 0 1 0.0, 1  0 1 0 0,0, 0 0 1 1 0, 0, 1 1 0 0 0, 0, 0 1 0 1 0, 0, 1 1 1 0 0, 0, 0 1 1 1 0, 0,1

TABLE EY Masking Step #2 (For Cases Where Input C = 0) Post Masked InputA Masked Input B Input C MaskingValue 0 0 0 0, 0, 0 0 1 0 0, 0, 0 1 0 01, 0, 0 1 1 0 1, 0, 0

TABLE EZ Masking Step #2 (For Cases Where Input C = 1) Post Masked InputA Masked Input B Input C MaskingValue 0 0 1 0, 0, 1 0 1 1 0, 1, 1 1 0 10, 0, 1 1 1 1 0, 1, 1

The example above shows how the results of an initial check can be usedto drive what masking is done at the next step in the process. In thecase that is illustrated, input C is first used to determine whetherinput A or B should be analyzed.

Although the invention is described herein with reference to thepreferred embodiment, one skilled in the art will readily appreciatethat other applications may be substituted for those set forth hereinwithout departing from the spirit and scope of the present invention.Accordingly, the invention should only be limited by the claims includedbelow.

1. In a network for high-speed transmission of digital data, saidnetwork comprising a memory, an apparatus for rapid differentiationbetween input data, the apparatus comprising: a module comprising afunctional element for each of adaptive, programmable, predictiverandomization of said digital data; and said module comprising at leastone programmable feedback shift register that is driven by said inputdata, wherein a final state of said at least one programmable shiftregister is used as an index into said memory to determine which if anyinput data pattern has been matched; wherein said functional element forpredictive randomization comprises means for permitting a plurality ofpossible randomization feedback path mappings to be maintained in saidmemory at any time; wherein said functional element for adaptiverandomization of said input data comprises means for adjusting saidrandomization feedback path mappings over time to handle changing inputdata patterns that are to be analyzed, said apparatus furthercomprising: means for maintaining statistics on substantially allpresently evaluated feedback randomization path mappings to determine abest randomization feedback path mapping, as well as any randomizationfeedback path mapping that is no longer usable; and means for quicklybringing substantially all of said input data patterns back to evaluateother possible randomization patterns when said randomization feedbackpath mapping is no longer usable; wherein said input data patternmatching effects data classification.
 2. The apparatus of claim 1,wherein said at least one shift register comprises a register having atleast two feedback paths that can be programmed to be enabled ordisabled.
 3. The apparatus of claim 2, wherein said at least twoprogrammable feedback paths are comprised such that output values fromone feedback path are uncorrelated to output values from anotherfeedback path.
 4. The apparatus of claim 3, wherein general probabilitytheory to be used to evaluate randomization of said input data.
 5. Theapparatus of claim 1, wherein said element for predictive randomizationcomprises means for pre-calculating said randomization for each possibleinput data pattern.
 6. The apparatus of claim 5, wherein saidpre-calculation is performed at a time that a new input data pattern isentered.
 7. The apparatus of claim 1, further comprising: means forperforming a full hardware calculation of expected randomization outputsfor each input that is applied.
 8. The apparatus of claim 7, wherein aplurality of randomizer feedback values are evaluated in real-time whena new input is applied.
 9. The apparatus of claim 1, further comprising:means for implementing sequential masking operations on said input datato accomplish sequential randomization of said input data patterns. 10.The apparatus of claim 9, further comprising: means for permittingeither of fixed or programmable masking of selected bit patterns withinsaid input data.
 11. The apparatus of claim 10, wherein said maskingoperations permit a user to pre-program a series of masking decisionsthat can result in a final input data pattern match.
 12. An apparatusfor rapid differentiation between input data comprised of a limitednumber of input data bits, comprising: a randomizer for providing ausable feedback randomization pattern, for a random set of receivedinputs, based upon an effective mapping of received input data patternsto output vectors, the randomizer comprising a primary randomizer formapping each received input data pattern to an output value, whereinsufficient randomizer feedbacks are simultaneously evaluated to providethat a usable feedback is substantially always available; and asecondary randomizer for differentiating between received input datapatterns that have been mapped to a same output value; wherein entriesin each of multiple data input patterns are different from each othersaid secondary randomizer comprising: means for permitting a set valueof multiple output cases where any of a plurality of input data patternsmap to a same output pattern, said means for permitting furtherincluding means for evaluating a plurality of paired, tripled orquadrupled output vectors from said primary randomizer.
 13. Theapparatus of claim 12, wherein for a given number of output states, agiven number of received input data patterns, and a given number ofmultiple outputs, said means for handling determines a probability thatany specific randomizer feedback maps said input data patterns into ausable set of output states.
 14. A method for ultra-high speed dataclassification, comprising the steps of: providing a data framercomprising an adaptive programmable randomizer, the adaptiveprogrammable randomizer comprising primary and secondary randomizers forframing input data; providing a complex circuit for permitting a user todifferentiate between a plurality of different patterns in said inputdata, said complex circuit performing the step of: performing serialmode classification of said input data to produce extremely fastcharacterization in a predictable timeframe by performing adaptiveprogrammable randomization to differentiate between input vectors;wherein said adaptive, programmable randomization comprises the stepsof: maintaining multiple input pattern mappings associated withdifferent primary and secondary randomizer equations; determining a bestrandomizer selection; deciding when to switch randomizer values; anddetermining when a randomizer value is no longer useful and an entirelynew mapping should be generated.
 15. An apparatus for ultra-high speeddata classification, comprising: a data framer; said data framercomprising an adaptive programmable randomizer, the adaptiveprogrammable randomizer comprising primary and secondary randomizers;and a complex circuit for controlling said adaptive programmablerandomizer, wherein said primary and secondary randomizers areprogrammably configured by said complex circuit; wherein said complexcircuit maintains multiple input pattern mappings associated withdifferent primary and secondary randomizer equations, determines a bestrandomizer selection, decides when to switch randomizer values, anddetermines when a randomizer value is no longer useful and an entirelynew mapping should be generated.
 16. The apparatus of claim 15, saiddata framer further comprising: a plurality of registers for setting upfeedback configurations for said randomizers.
 17. The apparatus of claim15, said data framer further comprising: a randomizer enable controlblock.
 18. The apparatus of claim 17, wherein a clock to said primaryand secondary randomizers is gated ON and OFF by an enable randomizersignal that is generated by said enable control block; and wherein saidenable randomizer signal is turned on at the start of a packet.
 19. Theapparatus of claim 15, said data framer further comprising: a maskingcontrol block that allows programmable, sequential, user controlledmasking of groups of user defined bits.
 20. The apparatus of claim 15,said data framer further comprising: an output register synchronizationand queue that assures that said primary randomizer, said secondaryrandomizer, feedback registers, and masking registers are stored foreach packet.
 21. The apparatus of claim 15, wherein said complex circuitcomprises any of the following: a microprocessor interface forcommunicating to a host processor system; a first memory interface forcommunicating with either of a stand alone memory or shared dual portmemory, for storing data patterns to be matched; a second memoryinterface for communicating with a dedicated memory that containsmappings for a plurality of primary and secondary randomizer settings;and an interface for communicating with said data framer.